forked from Github_Repos/cvw
42 lines
1.5 KiB
Systemverilog
42 lines
1.5 KiB
Systemverilog
///////////////////////////////////////////
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// ram1p1rwbe_64x44.sv
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//
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// Written: james.stine@okstate.edu 28 January 2023
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// Modified:
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//
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// Purpose: RAM wrapper for instantiating RAM IP
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ram1p1rwbe_64x44(
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input logic CLK,
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input logic CEB,
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input logic WEB,
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input logic [5:0] A,
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input logic [43:0] D,
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input logic [43:0] BWEB,
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output logic [43:0] Q
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);
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// replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
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TS1N28HPCPSVTB64X44M4SW sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
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//generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
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endmodule
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