forked from Github_Repos/cvw
168 lines
7.2 KiB
Systemverilog
168 lines
7.2 KiB
Systemverilog
///////////////////////////////////////////
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// pmpchecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 28 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and checks them against the
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// current values of the physical memory protection (PMP) registers.
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// Can raise an access fault on illegal reads, writes, and instruction
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// fetches.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pmpchecker (
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// input logic clk, reset, //*** it seems like clk, reset is also not needed here?
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input logic [31:0] HADDR,
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input logic [1:0] PrivilegeModeW,
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// *** ModelSim has a switch -svinputport which controls whether input ports
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// are nets (wires) or vars by default. The default setting of this switch is
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// `relaxed`, which means that signals are nets if and only if they are
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// scalars or one-dimensional vectors. Since this is a two-dimensional vector,
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// this will be understood as a var. However, if we don't supply the `var`
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// keyword, the compiler warns us that it's interpreting the signal as a var,
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// which we might not intend.
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// However, it's still bad form to pass 512 or 1024 signals across a module
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// boundary. It would be better to store the PMP address registers in a module
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// somewhere in the CSR hierarchy and do PMP checking _within_ that module, so
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// we don't have to pass around 16 whole registers.
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input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
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output logic PMPSquashBusAccess,
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output logic PMPInstrAccessFaultF,
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output logic PMPLoadAccessFaultM,
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output logic PMPStoreAccessFaultM
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);
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// Bit i is high when the address falls in PMP region i
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logic [`PMP_ENTRIES-1:0] Regions, FirstMatch;
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//logic [3:0] MatchedRegion;
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logic EnforcePMP;
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logic [7:0] PMPCFG [`PMP_ENTRIES-1:0];
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// Bit i is high when the address is greater than or equal to PMPADR[i]
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// Used for determining whether TOR PMP regions match
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logic [`PMP_ENTRIES-1:0] AboveRegion;
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// Bit i is high if PMP register i is non-null
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logic [`PMP_ENTRIES-1:0] ActiveRegion;
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logic [`PMP_ENTRIES-1:0] L_Bits, X_Bits, W_Bits, R_Bits;
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//logic InvalidExecute, InvalidWrite, InvalidRead;
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genvar i,j;
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pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[0][4:3]),
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.CurrentPMPAdr(PMPADDR_ARRAY_REGW[0]),
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.AdrAtLeastPreviousPMP(1'b1),
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.AdrAtLeastCurrentPMP(AboveRegion[0]),
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.Match(Regions[0]));
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assign ActiveRegion[0] = |PMPCFG[0][4:3];
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generate // *** only for PMP_ENTRIES > 0
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for (i = 1; i < `PMP_ENTRIES; i++) begin
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pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[i][4:3]),
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.CurrentPMPAdr(PMPADDR_ARRAY_REGW[i]),
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.AdrAtLeastPreviousPMP(AboveRegion[i-1]),
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.AdrAtLeastCurrentPMP(AboveRegion[i]),
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.Match(Regions[i]));
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assign ActiveRegion[i] = |PMPCFG[i][4:3];
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end
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endgenerate
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//assign Match = |Regions;
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// verilator lint_off UNOPTFLAT
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logic [`PMP_ENTRIES-1:0] NoLowerMatch;
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// assign NoLowerMatch[0] = 1;
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generate
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// verilator lint_off WIDTH
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for (j=0; j<`PMP_ENTRIES; j = j+8) begin
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assign {PMPCFG[j+7], PMPCFG[j+6], PMPCFG[j+5], PMPCFG[j+4],
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PMPCFG[j+3], PMPCFG[j+2], PMPCFG[j+1], PMPCFG[j]} = PMPCFG_ARRAY_REGW[j/8];
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end
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// verilator lint_on WIDTH
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for (i=0; i<`PMP_ENTRIES; i++) begin
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if (i==0) begin
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assign FirstMatch[i] = Regions[i];
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assign NoLowerMatch[i] = ~Regions[i];
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end else begin
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assign FirstMatch[i] = Regions[i] & NoLowerMatch[i];
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assign NoLowerMatch[i] = NoLowerMatch[i-1] & ~Regions[i];
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end
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assign L_Bits[i] = PMPCFG[i][7] & FirstMatch[i];
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assign X_Bits[i] = PMPCFG[i][2] & FirstMatch[i];
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assign W_Bits[i] = PMPCFG[i][1] & FirstMatch[i];
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assign R_Bits[i] = PMPCFG[i][0] & FirstMatch[i];
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end
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// verilator lint_on UNOPTFLAT
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endgenerate
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/* // *** extend to up to 64, fold bit extraction to avoid need for binary encoding of region
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always_comb
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casez (Regions)
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16'b???????????????1: MatchedRegion = 0;
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16'b??????????????10: MatchedRegion = 1;
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16'b?????????????100: MatchedRegion = 2;
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16'b????????????1000: MatchedRegion = 3;
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16'b???????????10000: MatchedRegion = 4;
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16'b??????????100000: MatchedRegion = 5;
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16'b?????????1000000: MatchedRegion = 6;
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16'b????????10000000: MatchedRegion = 7;
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16'b???????100000000: MatchedRegion = 8;
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16'b??????1000000000: MatchedRegion = 9;
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16'b?????10000000000: MatchedRegion = 10;
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16'b????100000000000: MatchedRegion = 11;
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16'b???1000000000000: MatchedRegion = 12;
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16'b??10000000000000: MatchedRegion = 13;
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16'b?100000000000000: MatchedRegion = 14;
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16'b1000000000000000: MatchedRegion = 15;
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default: MatchedRegion = 0; // Should only occur if there is no match
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endcase
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assign L_Bit = PMPCFG[MatchedRegion][7] && Match;
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assign X_Bit = PMPCFG[MatchedRegion][2] && Match;
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assign W_Bit = PMPCFG[MatchedRegion][1] && Match;
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assign R_Bit = PMPCFG[MatchedRegion][0] && Match;
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assign InvalidExecute = ExecuteAccessF && ~X_Bit;
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assign InvalidWrite = WriteAccessM && ~W_Bit;
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assign InvalidRead = ReadAccessM && ~R_Bit;*/
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// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
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assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L_Bits : |ActiveRegion;
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assign PMPInstrAccessFaultF = EnforcePMP && ExecuteAccessF && ~|X_Bits;
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assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM && ~|W_Bits;
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assign PMPLoadAccessFaultM = EnforcePMP && ReadAccessM && ~|R_Bits;
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assign PMPSquashBusAccess = PMPInstrAccessFaultF || PMPLoadAccessFaultM || PMPStoreAccessFaultM;
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endmodule
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