Shriya Nadgauda c66e63ff70 adding pipeline testing		2021-04-23 14:19:17 -04:00
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bin
config	greatly improved PLIC register interface	2021-04-22 11:22:01 -04:00
misc/tlb_toy	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ppa
regression	Remind people to run make allclean when a regression fails	2021-04-22 19:21:00 -04:00
src	Write PCM to TVAL registers	2021-04-22 16:17:57 -04:00
testbench	adding pipeline testing	2021-04-23 14:19:17 -04:00
testgen	adding pipeline testing	2021-04-23 14:19:17 -04:00
lint-wally	Pass lint-wally arguments to verilator	2021-04-22 13:39:20 -04:00