forked from Github_Repos/cvw
53 lines
1.5 KiB
Verilog
53 lines
1.5 KiB
Verilog
/* verilator lint_off STMTDLY */
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module testbench_fma16;
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reg clk, reset;
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reg [15:0] x, y, z, rexpected;
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wire [15:0] result;
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reg [7:0] ctrl;
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reg [3:0] flagsexpected;
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reg mul, add, negp, negz;
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reg [1:0] roundmode;
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reg [31:0] vectornum, errors;
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reg [75:0] testvectors[10000:0];
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// instantiate device under test
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fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result);
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// generate clock
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always
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begin
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clk = 1; #5; clk = 0; #5;
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end
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// at start of test, load vectors and pulse reset
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initial
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begin
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$readmemh("work/fmul_0.tv", testvectors);
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vectornum = 0; errors = 0;
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reset = 1; #22; reset = 0;
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end
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// apply test vectors on rising edge of clk
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always @(posedge clk)
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begin
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#1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum];
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{roundmode, mul, add, negp, negz} = ctrl[5:0];
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end
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// check results on falling edge of clk
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always @(negedge clk)
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if (~reset) begin // skip during reset
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if (result !== rexpected) begin // check result // *** should also add tests on flags eventually
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$display("Error: inputs %h * %h + %h", x, y, z);
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$display(" result = %h (%h expected)", result, rexpected);
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 'x) begin
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$display("%d tests completed with %d errors",
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vectornum, errors);
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$stop;
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end
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end
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endmodule
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