forked from Github_Repos/cvw
53 lines
2.1 KiB
Systemverilog
53 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// irom.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 30, 2022
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// Modified:
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//
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// Purpose: simple instruction ROM
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module irom(
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input logic clk, reset, ce,
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input logic [`XLEN-1:0] Adr,
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output logic [31:0] ReadData
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);
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localparam ADDR_WDITH = $clog2(`IROM_RANGE/8);
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localparam OFFSET = $clog2(`XLEN/8);
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logic [`XLEN-1:0] ReadDataFull;
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rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
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if (`XLEN == 32) assign ReadData = ReadDataFull;
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// have to delay Ardr[OFFSET-1] by 1 cycle
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else begin
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logic AdrD;
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flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
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assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0];
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end
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endmodule
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