forked from Github_Repos/cvw
38 lines
978 B
Python
38 lines
978 B
Python
# testgen-ADD-SUB.py
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#
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# David_Harris@hmc.edu 19 January 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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# libraries
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#import bitstream as bs
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#corners = [0, 1, 2, 0xFF, 0x624B3E97CC52DD14, 0x7FFFFFFFFFFFFFFE, 0x7FFFFFFFFFFFFFFF,
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# 0x8000000000000000, 0x8000000000000001, 0xC365DDEB9173AB42, 0xFFFFFFFFFFFFFFFE, 0xFFFFFFFFFFFFFFFF]
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corners = [0, 1, 2, 255]
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testname = "ADD-SUB"
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fname = "WALLY-" + testname
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testnum = 0;
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# Testcase 0: rs1:x31(0x10fd3dedadea5195), rs2:x16(0xdf7f3844121bcc23), result rd:x1(0xf07c7631c0061db8)
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# li x16, MASK_XLEN(0xdf7f3844121bcc23)
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#li x31, MASK_XLEN(0x10fd3dedadea5195)
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# add x1, x31, x16
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# sd x1, 0(x6)
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#RVTEST_IO_ASSERT_GPR_EQ(x7, x1, 0xf07c7631c0061db8)
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f = open(fname, "w")
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for a in corners:
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for b in corners:
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tc = "# Testcase " + str(testnum
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f.write(tc)
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line = "li x1, MASK_XLEN(" + str(a) + ")"
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f.write(line)
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testnum = testnum+1
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f.close() |