forked from Github_Repos/cvw
143 lines
6.2 KiB
Systemverilog
143 lines
6.2 KiB
Systemverilog
///////////////////////////////////////////
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// datapath.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Integer Datapath
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module datapath (
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input logic clk, reset,
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// Decode stage signals
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input logic [2:0] ImmSrcD,
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input logic [31:0] InstrD,
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input logic [2:0] Funct3E,
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// Execute stage signals
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input logic StallE, FlushE,
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input logic [1:0] ForwardAE, ForwardBE,
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input logic [2:0] ALUControlE,
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input logic ALUSrcAE, ALUSrcBE,
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input logic ALUResultSrcE,
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input logic JumpE,
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input logic IllegalFPUInstrE,
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input logic [`XLEN-1:0] FWriteDataE,
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCLinkE,
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output logic [2:0] FlagsE,
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output logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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// Memory stage signals
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input logic StallM, FlushM,
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input logic FWriteIntM,
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input logic [`XLEN-1:0] FIntResM,
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output logic [`XLEN-1:0] SrcAM,
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output logic [`XLEN-1:0] WriteDataM,
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// Writeback stage signals
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input logic StallW, FlushW,
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input logic RegWriteW,
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input logic SquashSCW,
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input logic [2:0] ResultSrcW,
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output logic [`XLEN-1:0] ReadDataW,
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// input logic [`XLEN-1:0] PCLinkW,
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input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MulDivResultW,
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// Hazard Unit signals
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output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
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output logic [4:0] RdE, RdM, RdW
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);
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// Fetch stage signals
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// Decode stage signals
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logic [`XLEN-1:0] RD1D, RD2D;
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logic [`XLEN-1:0] ExtImmD;
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logic [4:0] RdD;
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// Execute stage signals
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logic [`XLEN-1:0] RD1E, RD2E;
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logic [`XLEN-1:0] ExtImmE;
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// logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
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logic [`XLEN-1:0] SrcAE, SrcBE;
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logic [`XLEN-1:0] SrcAE2, SrcBE2;
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logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
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logic [`XLEN-1:0] WriteDataE;
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// Memory stage signals
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logic [`XLEN-1:0] IEUResultM;
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logic [`XLEN-1:0] ResultM;
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// Writeback stage signals
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logic [`XLEN-1:0] SCResultW;
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logic [`XLEN-1:0] WriteDataW;
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logic [`XLEN-1:0] ResultW;
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// Decode stage
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assign Rs1D = InstrD[19:15];
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assign Rs2D = InstrD[24:20];
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assign RdD = InstrD[11:7];
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regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
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extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
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// Execute stage pipeline register and logic
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flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
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flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, RD2D, RD2E);
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flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE);
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flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
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flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
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flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
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mux3 #(`XLEN) faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
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mux3 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
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mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
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mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
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// Memory stage pipeline register
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flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
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flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
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flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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// Writeback stage pipeline register and logic
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flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
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flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
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flopen #(`XLEN) ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW));
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mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);
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// floating point interactions: fcvt, fp stores
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generate
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if (`F_SUPPORTED) begin:fpmux
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mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
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mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
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end else begin
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assign ResultM = IEUResultM;
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assign WriteDataE = ForwardedSrcBE;
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end
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endgenerate
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// handle Store Conditional result if atomic extension supported
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generate
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if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
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else assign SCResultW = 0;
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endgenerate
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endmodule
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