forked from Github_Repos/cvw
313 lines
10 KiB
Python
313 lines
10 KiB
Python
#!/usr/bin/python3
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##################################
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# testgen-IE.py
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#
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# ushakya@hmc.edu 31 March 2021
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# Modified: 4 April 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# functions
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##################################
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def writeTrapHandlers(storecmd):
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global testnum
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[reg1, reg2, reg3] = [30, 29, 28]
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[reg4, reg5] = [27, 26]
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lines = "\n# Trap Handler: Machine Timer Interupt\n"
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lines += "_timerM_trap_handler:\n"
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lines += "li x" + str(reg1) + ", MASK_XLEN(0x2A)\n"
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lines += "la x" + str(reg2) + ", 0x2004000\n"
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lines += str(storecmd) + " x" + str(reg1) + ", 0(x" + str(reg2) + ")\n"
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lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
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lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Supervisor Timer Interupt\n"
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lines += "_timerS_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x20)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: User Timer Interupt\n"
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lines += "_timerU_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x10)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Machine Software Interupt\n"
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lines += "_softwareM_trap_handler:\n"
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lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
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lines += "la x" + str(reg2) + ", 0x2000000\n"
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lines += str(storecmd) + " x" + str(reg1) + ", 0(x" + str(reg2) + ")\n"
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lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
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lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Supervisor Software Interupt\n"
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lines += "_softwareS_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x2)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: User Software Interupt\n"
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lines += "_softwareU_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x1)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Machine External Interupt\n"
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lines += "_externalM_trap_handler:\n"
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#lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
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#lines += "la x" + str(reg2) + ", 0x2000000\n"
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#lines += str(storecmd) + " x" + str(reg1) + ", 0(x" + str(reg2) + ")\n"
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lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
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lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Supervisor External Interupt\n"
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lines += "_externalS_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x200)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: User External Interupt\n"
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lines += "_externalU_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x100)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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f.write(lines)
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def getInteruptEnableValues():
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if test == "timerM":
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mstatusE = 0x8
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mieE = 0x80
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elif test == "timerS":
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mstatusE = 0x2
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mieE = 0x20
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elif test == "timerU":
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mstatusE = 0x1
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mieE = 0x10
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elif test == "softwareM":
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mstatusE = 0x8
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mieE = 0x8
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elif test == "softwareS":
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mstatusE = 0x2
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mieE = 0x2
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elif test == "softwareU":
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mstatusE = 0x1
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mieE = 0x1
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elif test == "externalM":
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mstatusE = 0x8
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mieE = 0x800
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elif test == "externalS":
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mstatusE = 0x2
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mieE = 0x200
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elif test == "externalU":
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mstatusE = 0x1
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mieE = 0x100
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return [mstatusE, mieE]
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def getMcause():
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b = 1 << (xlen-1)
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if test == "timerM":
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b = b + 0x7
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elif test == "timerS":
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b = b + 0x5
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elif test == "timerU":
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b = b + 0x4
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elif test == "softwareM":
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b = b + 0x3
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elif test == "softwareS":
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b = b + 0x1
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elif test == "softwareU":
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b = b
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elif test == "externalM":
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b = b + 0xB
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elif test == "externalS":
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b = b + 0x9
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elif test == "externalU":
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b = b + 0x8
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return b
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def writeVectors(a, xlen, storecmd):
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global testnum
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[reg1, reg2, reg3] = [1, 2, 3]
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[reg5, reg8] = [5, 8]
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[reg9, reg10, reg11, reg12] = [9, 10, 11, 12]
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lines = f"\n# Testcase {testnum}: {test} Interupt\n"
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# mcause code
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expected = getMcause()
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(expected) + ")\n"
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if (testnum == 0): expected = 0
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[mstatusE, mieE] = getInteruptEnableValues()
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# set interupt enable bit in mstatus
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lines += "li x" + str(reg3) + ", MASK_XLEN(" + str(mstatusE) + ")\n"
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lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
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# set timer interupt enable bit in mie
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lines += "li x" + str(reg9) + ", MASK_XLEN(" + str(mieE) + ")\n"
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lines += "csrrs x0, mie, x" + str(reg3) + "\n"
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# Save and set trap handler address for interrupt
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lines += "la x" + str(reg5) + ", _" + test + "_trap_handler\n"
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# save orignal mtvec address
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lines += "csrrw x" + str(reg12) + ", mtvec, x" + str(reg5) + "\n"
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# cause timer interupt
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if test == "timerM":
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lines += "li x" + str(reg8) + ", MASK_XLEN(0)\n"
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lines += str(storecmd) + " x" + str(reg8) + ", " + str(wordsize*testnum)+ "(x6)\n"
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lines += "la x" + str(reg8) + ", 0x2004000\n"
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lines += "li x" + str(reg3) + ", MASK_XLEN(0)\n"
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# save old value of mtimecmp and then set mtimecmp to zero
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lines += "lw x" + str(reg11) + ", 0(x" + str(reg8) + ")\n"
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lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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elif test == "timerS":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x20)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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elif test == "timerU":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x10)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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# cause software interupt
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if test == "softwareM":
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lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
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lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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elif test == "softwareS":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x2)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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elif test == "softwareU":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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# cause external interupt
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# Not sure how to cause an external machine interupt yet
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# will writing to PLIC just cause it? (where is the ExtIntM located in PLIC)
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#if test == "externalM":
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#lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
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#lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
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#lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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if test == "externalS":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x200)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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elif test == "externalU":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x100)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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#lines += "wfi\n" # wait for interupt to be taken
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lines += "nop\nnop\n"
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lines += "csrrw " + " x" + str(reg2) + ", mcause, x" + str(reg1) + "\n"
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# reset mtvec
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lines += "csrrw x0, mtvec, x" + str(reg12) + "\n"
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lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
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lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg2) +", "+formatstr.format(expected)+")\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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tests = ["timerM"] #, "timerS", "timerU", "softwareM", "softwareS", "softwareU"]
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author = "ushakya@hmc.edu"
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xlens = [64, 32]
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numrand = 100;
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# setup
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seed(0) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for test in tests:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-IE"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# print directed and random test vectors
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for i in range(0,numrand):
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a = getrandbits(xlen)
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writeVectors(a, xlen, storecmd)
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writeTrapHandlers(storecmd)
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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