forked from Github_Repos/cvw
47 lines
1.5 KiB
ArmAsm
47 lines
1.5 KiB
ArmAsm
///////////////////////////////////////////
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// priv.S
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//
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// Written: David_Harris@hmc.edu 23 March 2023
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//
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// Purpose: Test coverage for EBU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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# switch to supervisor mode
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li a0, 1
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ecall
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# Test read to stimecmp fails when MCOUNTEREN_TM is not set
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addi t0, zero, 0
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csrr t0, stimecmp
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# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
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li t0, 0
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csrw stval, t0
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csrw scause, t0
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csrw sepc, t0
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csrw stimecmp, t0
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j done
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