forked from Github_Repos/cvw
0b1e59d075
Updated PCNextF so it points to the correct PC after icache invalidate. Build root crashes with PCW mismatch and invalid register writes.
50 lines
1.5 KiB
Plaintext
50 lines
1.5 KiB
Plaintext
# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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switch $argc {
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0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt -fsmdebug +acc -gDEBUG=1 work.testbench -o workopt
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vsim workopt -fsmdebug
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#profile on
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do wave.do
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add log -r /*
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-- Run the Simulation
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#run 1000
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run -all
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#quit
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