forked from Github_Repos/cvw
71 lines
3.1 KiB
Systemverilog
71 lines
3.1 KiB
Systemverilog
///////////////////////////////////////////
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// pmachecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and identifies attributes of
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// the memory region accessed.
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// Can report illegal accesses to the trap unit and cause a fault.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pmachecker (
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// input logic clk, reset, // *** unused in this module and all sub modules.
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [1:0] Size,
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
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output logic Cacheable, Idempotent, AtomicAllowed,
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output logic PMASquashBusAccess,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAccessFaultM
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);
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logic PMAAccessFault;
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logic AccessRW, AccessRWX, AccessRX;
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logic [6:0] SelRegions;
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// Determine what type of access is being made
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assign AccessRW = ReadAccessM | WriteAccessM;
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assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
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assign AccessRX = ReadAccessM | ExecuteAccessF;
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// Determine which region of physical memory (if any) is being accessed
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adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
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// Only RAM memory regions are cacheable
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assign Cacheable = SelRegions[5] | SelRegions[4];
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assign Idempotent = SelRegions[4];
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assign AtomicAllowed = SelRegions[4];
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// Detect access faults
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assign PMAAccessFault = SelRegions[6] & AccessRWX;
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assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
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assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
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assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
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assign PMASquashBusAccess = PMAAccessFault;
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endmodule
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