forked from Github_Repos/cvw
cc48cdc97b
If the instruction address spilled across two pages and the second page misses the TLB, the HPTW received a tlb miss at the address of the first page rather than the second. After the walk the TLB was updated with the PTE from the first page at the address of the second page. Example bug Instruction PCF = 0x2ffe First page in 0x2ffe and second page in 0x3000. The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000. TLB is updated with PTE from 0x2ffe at 0x3000. |
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| .. | ||
| functionName.sv | ||
| instrNameDecTB.sv | ||
| instrTrackerTB.sv | ||