forked from Github_Repos/cvw
63 lines
1.4 KiB
ArmAsm
63 lines
1.4 KiB
ArmAsm
.section .text
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.global simple_csrbr_test
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.type simple_csrbr_test, @function
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simple_csrbr_test:
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# step 1 enable the performance counters
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# by default the hardware enables all performance counters
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# however we will eventually want to manually enable incase
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# some other code disables them
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# br count is counter 5
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# br mp count is counter 4
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li t0, 0x30
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csrrc x0, 0x320, t0 # clear bits 4 and 5 of inhibit register.
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# step 2 read performance counters into general purpose registers
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csrrw t2, 0xB05, x0 # t2 = BR COUNT (perf count 5)
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csrrw t3, 0xB04, x0 # t3 = BRMP COUNT (perf count 4)
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# step 3 simple loop to show the counters are updated.
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li t0, 0 # this is the loop counter
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li t1, 100 # this is the loop end condition
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# for(t1 = 0; t1 < t0; t1++);
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loop:
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addi t0, t0, 1
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blt t0, t1, loop
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loop_done:
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# step 2 read performance counters into general purpose registers
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csrrw t4, 0xB05, x0 # t4 = BR COUNT (perf count 5)
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csrrw t5, 0xB04, x0 # t5 = BRMP COUNT (perf count 4)
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sub t2, t4, t2 # this is the number of branch instructions committed.
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sub t3, t5, t3 # this is the number of branch mispredictions committed.
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# now check if the branch count equals 100 and if the branch
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bne t4, t2, fail
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li t5, 3
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bne t3, t5, fail
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pass:
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li a0, 0
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done:
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li t0, 0x30
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csrrs x0, 0x320, t0 # set bits 4 and 5
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ecall
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ret
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fail:
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li a0, -1
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j done
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.data
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sample_data:
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.int 0
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