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461b9d370d
cvw
/
pipelined
/
testbench
History
DTowersM
dedfadbb14
Merge branch 'main' of
https://github.com/davidharrishmc/riscv-wally
2022-08-31 00:18:04 +00:00
..
common
Added WFI to the testbench instruction name decoder
2022-04-14 17:12:11 +00:00
fp
generating all testfloat vectors
2022-04-04 17:17:12 +00:00
sdc
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
testbench-fp.sv
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
testbench-linux.sv
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 16:01:02 -05:00
testbench.sv
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
2022-08-26 21:05:20 -07:00
tests-fp.vh
postprocessing unit created and passing all tests
2022-06-13 22:47:51 +00:00
tests.vh
fixed qrduino keyerror in embench test
2022-08-31 00:17:58 +00:00
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