forked from Github_Repos/cvw
367 lines
12 KiB
Systemverilog
367 lines
12 KiB
Systemverilog
///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu 13 January 2022
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// Modified:
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module srtradix4 (
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input logic clk,
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input logic DivStart,
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input logic [`NE-1:0] XExpE, YExpE,
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input logic [`NF:0] XManE, YManE,
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic XZeroE,
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic DivDone,
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output logic [`DIVLEN+2:0] Quot,
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output logic [`XLEN-1:0] Rem, // *** later handle integers
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output logic [`NE:0] DivCalcExpE
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);
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// logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [3:0] q;
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logic [`NE:0] DivCalcExp;
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logic [`DIVLEN:0] X;
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logic [`DIVLEN-1:0] Dpreproc;
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logic [`DIVLEN+3:0] WS, WSA, WSN;
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logic [`DIVLEN+3:0] WC, WCA, WCN;
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logic [`DIVLEN+3:0] D, DBar, D2, DBar2, Dsel;
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logic [$clog2(`XLEN+1)-1:0] intExp;
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logic intSign;
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srtpreproc preproc(SrcA, SrcB, XManE, YManE, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign);
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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// - assumed one is added here since all numbers are normlaized
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// *** wait what about zero? is that specal case? can the divider handle it?
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// - when the start signal is asserted X and 0 are loaded into WS and WC
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// - otherwise load WSA into the flipflop
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// *** what does N and A stand for?
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// *** change shift amount for radix4
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mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+1:0], 2'b0}, {3'b000, X}, DivStart, WSN);
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flop #(`DIVLEN+4) wsflop(clk, WSN, WS);
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mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+1:0], 2'b0}, {`DIVLEN+4{1'b0}}, DivStart, WCN);
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flop #(`DIVLEN+4) wcflop(clk, WCN, WC);
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flopen #(`DIVLEN+4) dflop(clk, DivStart, {4'b0001, Dpreproc}, D);
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// *** change this for radix 4 - generate w/ stine code
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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qsel4 qsel4(.D, .WS, .WC, .q);
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// Store the expoenent and sign until division is DivDone
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flopen #(`NE+1) expflop(clk, DivStart, DivCalcExp, DivCalcExpE);
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// Divisor Selection logic
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// *** radix 4 change to choose -2 to 2
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// - choose the negitive version of what's being selected
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assign DBar = ~D;
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assign DBar2 = {~D[`DIVLEN+2:0], 1'b1};
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assign D2 = {D[`DIVLEN+2:0], 1'b0};
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always_comb
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case (q)
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4'b1000: Dsel = DBar2;
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4'b0100: Dsel = DBar;
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4'b0000: Dsel = {(`DIVLEN+4){1'b0}};
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4'b0010: Dsel = D;
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4'b0001: Dsel = D2;
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default: Dsel = {`DIVLEN+4{1'bx}};
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endcase
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, |q[3:2], WSA, WCA);
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//*** change for radix 4
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otfc4 otfc4(.clk, .DivStart, .q, .Quot);
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expcalc expcalc(.XExpE, .YExpE, .XZeroE, .DivCalcExp);
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divcounter divcounter(clk, DivStart, DivDone);
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endmodule
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////////////////
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// Submodules //
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////////////////
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/////////////
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// counter //
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/////////////
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module divcounter(input logic clk,
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input logic DivStart,
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output logic DivDone);
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logic [5:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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DivDone = 0;
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if (count == `DIVLEN/2+1) DivDone <= #1 1;
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else if (DivDone | DivStart) DivDone <= #1 0;
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if (DivStart) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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module qsel4 (
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input logic [`DIVLEN+3:0] D,
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input logic [`DIVLEN+3:0] WS, WC,
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output logic [3:0] q
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);
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logic [6:0] Wmsbs;
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logic [7:0] PreWmsbs;
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logic [2:0] Dmsbs;
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assign PreWmsbs = WC[`DIVLEN+3:`DIVLEN-4] + WS[`DIVLEN+3:`DIVLEN-4];
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assign Wmsbs = PreWmsbs[7:1];
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assign Dmsbs = D[`DIVLEN-1:`DIVLEN-3];
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// D = 0001.xxx...
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// Dmsbs = | |
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// W = xxxx.xxx...
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// Wmsbs = | |
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logic [3:0] QSel4[1023:0];
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initial begin
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integer d, w, i, w2;
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for(d=0; d<8; d++)
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for(w=0; w<128; w++)begin
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i = d*128+w;
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w2 = w-128*(w>=64); // convert to two's complement
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case(d)
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0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-4) QSel4[i] = 4'b0000;
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else if(w2>=-13) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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1: if(w2>=14) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-6) QSel4[i] = 4'b0000;
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else if(w2>=-15) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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2: if(w2>=15) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-6) QSel4[i] = 4'b0000;
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else if(w2>=-16) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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3: if(w2>=16) QSel4[i] = 4'b1000;
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else if(w2>=4) QSel4[i] = 4'b0100;
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else if(w2>=-6) QSel4[i] = 4'b0000;
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else if(w2>=-18) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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4: if(w2>=18) QSel4[i] = 4'b1000;
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else if(w2>=6) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-20) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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5: if(w2>=20) QSel4[i] = 4'b1000;
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else if(w2>=6) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-20) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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6: if(w2>=20) QSel4[i] = 4'b1000;
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else if(w2>=8) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-22) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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7: if(w2>=24) QSel4[i] = 4'b1000;
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else if(w2>=8) QSel4[i] = 4'b0100;
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else if(w2>=-8) QSel4[i] = 4'b0000;
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else if(w2>=-24) QSel4[i] = 4'b0010;
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else QSel4[i] = 4'b0001;
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endcase
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end
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end
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assign q = QSel4[{Dmsbs,Wmsbs}];
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endmodule
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///////////////////
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// Preprocessing //
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///////////////////
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module srtpreproc (
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [`NF:0] XManE, YManE,
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [`DIVLEN:0] X,
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output logic [`DIVLEN-1:0] Dpreproc,
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output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
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output logic intSign // Quotient integer sign
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);
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// logic [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB;
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// logic [`XLEN-1:0] PosA, PosB;
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// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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logic [`DIVLEN:0] PreprocA, PreprocX;
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logic [`DIVLEN-1:0] PreprocB, PreprocY;
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// assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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// assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
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// lzc #(`XLEN) lzcA (PosA, zeroCntA);
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// lzc #(`XLEN) lzcB (PosB, zeroCntB);
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// assign ExtraA = {PosA, {`DIVLEN-`XLEN{1'b0}}};
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// assign ExtraB = {PosB, {`DIVLEN-`XLEN{1'b0}}};
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// assign PreprocA = ExtraA << zeroCntA;
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// assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {XManE, {`DIVLEN-`NF{1'b0}}};
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assign PreprocY = {YManE[`NF-1:0], {`DIVLEN-`NF{1'b0}}};
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assign X = Int ? PreprocA : PreprocX;
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assign Dpreproc = Int ? PreprocB : PreprocY;
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// assign intExp = zeroCntB - zeroCntA + 1;
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// assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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endmodule
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///////////////////////////////////
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// On-The-Fly Converter, Radix 2 //
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///////////////////////////////////
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module otfc4 (
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input logic clk,
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input logic DivStart,
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input logic [3:0] q,
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output logic [`DIVLEN+2:0] Quot
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);
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// The on-the-fly converter transfers the quotient
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// bits to the quotient as they come.
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//
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// This code follows the psuedocode presented in the
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// floating point chapter of the book. Right now,
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// it is written for Radix-4 division.
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//
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// QM is Q-1. It allows us to write negative bits
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// without using a costly CPA.
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logic [`DIVLEN+2:0] QM, QNext, QMNext, QMux, QMMux;
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// QR and QMR are the shifted versions of Q and QM.
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// They are treated as [N-1:r] size signals, and
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// discard the r most significant bits of Q and QM.
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logic [`DIVLEN:0] QR, QMR;
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// if starting a new divison set Q to 0 and QM to -1
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mux2 #(`DIVLEN+3) Qmux(QNext, {`DIVLEN+3{1'b0}}, DivStart, QMux);
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mux2 #(`DIVLEN+3) QMmux(QMNext, {`DIVLEN+3{1'b1}}, DivStart, QMMux);
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flop #(`DIVLEN+3) Qreg(clk, QMux, Quot);
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flop #(`DIVLEN+3) QMreg(clk, QMMux, QM);
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// shift Q (quotent) and QM (quotent-1)
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// if q = 2 Q = {Q, 10} QM = {Q, 01}
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// else if q = 1 Q = {Q, 01} QM = {Q, 00}
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// else if q = 0 Q = {Q, 00} QM = {QM, 11}
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// else if q = -1 Q = {QM, 11} QM = {QM, 10}
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// else if q = -2 Q = {QM, 10} QM = {QM, 01}
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// *** how does the 0 concatination numbers work?
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always_comb begin
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QR = Quot[`DIVLEN:0];
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QMR = QM[`DIVLEN:0]; // Shift Q and QM
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if (q[3]) begin // +2
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QNext = {QR, 2'b10};
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QMNext = {QR, 2'b01};
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end else if (q[2]) begin // +1
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QNext = {QR, 2'b01};
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QMNext = {QR, 2'b00};
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end else if (q[1]) begin // -1
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QNext = {QMR, 2'b11};
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QMNext = {QMR, 2'b10};
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end else if (q[0]) begin // -2
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QNext = {QMR, 2'b10};
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QMNext = {QMR, 2'b01};
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end else begin // 0
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QNext = {QR, 2'b00};
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QMNext = {QMR, 2'b11};
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end
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end
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// Quot is in the range [.5, 2) so normalize the result if nesissary
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// assign Quot = Q[`DIVLEN+2] ? Q[`DIVLEN+1:2] : Q[`DIVLEN:1];
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endmodule
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/////////
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// csa //
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/////////
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module csa #(parameter N=69) (
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input logic [N-1:0] in1, in2, in3,
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input logic cin,
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output logic [N-1:0] out1, out2
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);
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// This block adds in1, in2, in3, and cin to produce
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// a result out1 / out2 in carry-save redundant form.
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// cin is just added to the least significant bit and
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// is Startuired to handle adding a negative divisor.
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// Fortunately, the carry (out2) is shifted left by one
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// bit, leaving room in the least significant bit to
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// insert cin.
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assign #1 out1 = in1 ^ in2 ^ in3;
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assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) |
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(in2[N-2:0] & in3[N-2:0]), cin};
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endmodule
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//////////////
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// expcalc //
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//////////////
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module expcalc(
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input logic [`NE-1:0] XExpE, YExpE,
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input logic XZeroE,
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output logic [`NE:0] DivCalcExp
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);
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assign DivCalcExp = (XExpE - YExpE + (`NE)'(`BIAS))&{`NE+1{~XZeroE}};
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endmodule
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