forked from Github_Repos/cvw
80 lines
2.5 KiB
Systemverilog
80 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// endianswap.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 7 May 2022
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// Modified: 18 January 2023
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//
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// Purpose: Swap byte order for Big-Endian accesses
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//
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// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module endianswap #(parameter LEN=`XLEN) (
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input logic BigEndianM,
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input logic [LEN-1:0] a,
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output logic [LEN-1:0] y
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);
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if(LEN == 128) begin
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always_comb
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if (BigEndianM) begin // swap endianness
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y[127:120] = a[7:0];
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y[119:112] = a[15:8];
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y[111:104] = a[23:16];
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y[103:96] = a[31:24];
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y[95:88] = a[39:32];
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y[87:80] = a[47:40];
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y[79:72] = a[55:48];
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y[71:64] = a[63:56];
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y[63:56] = a[71:64];
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y[55:48] = a[79:72];
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y[47:40] = a[87:80];
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y[39:32] = a[95:88];
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y[31:24] = a[103:96];
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y[23:16] = a[111:104];
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y[15:8] = a[119:112];
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y[7:0] = a[127:120];
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end else y = a;
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end else if(LEN == 64) begin
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always_comb
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if (BigEndianM) begin // swap endianness
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y[63:56] = a[7:0];
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y[55:48] = a[15:8];
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y[47:40] = a[23:16];
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y[39:32] = a[31:24];
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y[31:24] = a[39:32];
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y[23:16] = a[47:40];
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y[15:8] = a[55:48];
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y[7:0] = a[63:56];
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end else y = a;
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end else begin
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always_comb
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if (BigEndianM) begin
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y[31:24] = a[7:0];
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y[23:16] = a[15:8];
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y[15:8] = a[23:16];
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y[7:0] = a[31:24];
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end else y = a;
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end
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endmodule
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