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Configurable RISC-V Processor
1,773 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
4139f27d10
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David Harris 4139f27d10 Divider FSM simplification
2021-10-10 22:24:14 -07:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
wally-pipelined Divider FSM simplification 2021-10-10 22:24:14 -07:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Added git things to make it all a little nicer and synthesis work. 2021-09-15 12:15:53 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor