forked from Github_Repos/cvw
102 lines
3.6 KiB
Systemverilog
102 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// mul_cs.sv
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//
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// Written: james.stine@okstate.edu 17 October 2021
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// Modified:
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//
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// Purpose: Carry/Save Multiplier output with Wallace Reduction
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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module mult_cs #(parameter WIDTH = 8)
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(a, b, tc, sum, carry);
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input logic [WIDTH-1:0] a;
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input logic [WIDTH-1:0] b;
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input logic tc;
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output logic [2*WIDTH-1:0] sum;
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output logic [2*WIDTH-1:0] carry;
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// PP array
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logic [2*WIDTH-1:0] pp_array [0:WIDTH-1];
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logic [2*WIDTH-1:0] next_pp_array [0:WIDTH-1];
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logic [2*WIDTH-1:0] tmp_sum, tmp_carry;
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logic [2*WIDTH-1:0] temp_pp;
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logic [2*WIDTH-1:0] tmp_pp_carry;
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logic [WIDTH-1:0] temp_b;
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logic temp_bitgroup;
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integer bit_pair, height, i;
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always_comb
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begin
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// For each multiplicand PP generation
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for (bit_pair=0; bit_pair < WIDTH; bit_pair=bit_pair+1)
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begin
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// Shift to the right via P&H
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temp_b = (b >> (bit_pair));
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temp_bitgroup = temp_b[0];
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// PP generation
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case (temp_bitgroup)
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1'b0 : temp_pp = {2*WIDTH-1{1'b0}};
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1'b1 : temp_pp = a;
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default : temp_pp = {2*WIDTH-1{1'b0}};
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endcase
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// Shift to the left via P&H
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temp_pp = temp_pp << (bit_pair);
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pp_array[bit_pair] = temp_pp;
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end
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// Height is multiplier
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height = WIDTH;
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// Wallace Tree PP reduction
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while (height > 2)
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begin
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for (i=0; i < (height/3); i=i+1)
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begin
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next_pp_array[i*2] = pp_array[i*3]^pp_array[i*3+1]^pp_array[i*3+2];
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tmp_pp_carry = (pp_array[i*3] & pp_array[i*3+1]) |
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(pp_array[i*3+1] & pp_array[i*3+2]) |
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(pp_array[i*3] & pp_array[i*3+2]);
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next_pp_array[i*2+1] = tmp_pp_carry << 1;
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end
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// Reasssign not divisible by 3 rows to next_pp_array
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if ((height % 3) > 0)
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begin
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for (i=0; i < (height % 3); i=i+1)
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next_pp_array[2 * (height/3) + i] = pp_array[3 * (height/3) + i];
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end
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// Put back values in pp_array to start again
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for (i=0; i < WIDTH; i=i+1)
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pp_array[i] = next_pp_array[i];
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// Reduce height
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height = height - (height/3);
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end
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// Sum is first row in reduced array
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tmp_sum = pp_array[0];
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// Carry is second row in reduced array
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tmp_carry = pp_array[1];
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end
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assign sum = tmp_sum;
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assign carry = tmp_carry;
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endmodule // mult_cs
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