forked from Github_Repos/cvw
63 lines
2.7 KiB
Systemverilog
63 lines
2.7 KiB
Systemverilog
///////////////////////////////////////////
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// lrsc.sv
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//
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// Written: David_Harris@hmc.edu 17 July 2021
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// Modified:
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//
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// Purpose: Load Reserved / Store Conditional unit
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// Track the reservation and squash the store if it fails
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lrsc(
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input logic clk, reset,
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input logic StallW,
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input logic MemReadM,
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input logic [1:0] PreLSURWM,
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output logic [1:0] LSURWM,
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input logic [1:0] LSUAtomicM,
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input logic [`PA_BITS-1:0] PAdrM, // from mmu to dcache
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output logic SquashSCW
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);
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// Handle atomic load reserved / store conditional
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic lrM, scM, WriteAdrMatchM;
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logic SquashSCM;
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assign lrM = MemReadM & LSUAtomicM[0];
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assign scM = PreLSURWM[0] & LSUAtomicM[0];
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assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
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assign SquashSCM = scM & ~WriteAdrMatchM;
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assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
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always_comb begin // ReservationValidM (next value of valid reservation)
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if (lrM) ReservationValidM = 1; // set valid on load reserve
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// if we implement multiple harts invalidate reservation if another hart stores to this reservation.
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else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
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else ReservationValidM = ReservationValidW; // otherwise don't change valid
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end
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flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
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flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
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endmodule
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