forked from Github_Repos/cvw
131 lines
3.4 KiB
Plaintext
131 lines
3.4 KiB
Plaintext
**/work*
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**/wally_*.log
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.nfs*
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__pycache__/
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.vscode/
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#External repos
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addins/riscv-arch-test/Makefile.include
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addins/riscv-tests/target
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addins/TestFloat-3e/build/Linux-x86_64-GCC/*
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benchmarks/embench/wally*.json
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#vsim work files to ignore
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transcript
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vsim.wlf
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pipelined/wlft*
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wlft*
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/imperas-riscv-tests/FunctionRadix_32.addr
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/imperas-riscv-tests/FunctionRadix_64.addr
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/imperas-riscv-tests/FunctionRadix.addr
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/imperas-riscv-tests/ProgramMap.txt
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/imperas-riscv-tests/logs
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*.o
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*.d
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*.vstf
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testsBP/*/*/*.elf*
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testsBP/*/OBJ/*
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testsBP/*/*.a
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tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
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tests/riscof/riscof_work/
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tests/riscof/config32.ini
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tests/riscof/config32e.ini
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tests/riscof/config64.ini
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tests/linux-testgen/linux-testvectors/*
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!tests/linux-testgen/linux-testvectors/tvCopier.py
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!tests/linux-testgen/linux-testvectors/tvLinker.sh
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!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
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tests/linux-testgen/buildroot
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tests/linux-testgen/buildroot-image-output
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tests/linux-testgen/buildroot-config-src/main.config.old
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tests/linux-testgen/buildroot-config-src/linux.config.old
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tests/linux-testgen/buildroot-config-src/busybox.config.old
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pipelined/regression/slack-notifier/slack-webhook-url.txt
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pipelined/regression/logs
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fpga/generator/IP
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fpga/generator/vivado.*
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fpga/generator/.Xil/*
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fpga/generator/WallyFPGA*
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fpga/generator/reports/
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fpga/generator/*.log
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fpga/generator/*.jou
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*.objdump*
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*.signature.output
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examples/asm/sumtest/sumtest
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examples/asm/example/example
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examples/C/sum/sum
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examples/C/fir/fir
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examples/fp/softfloat_demo/softfloat_demo
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examples/fp/fpcalc/fpcalc
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pipelined/src/fma/fma16_testgen
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linux/devicetree/debug/*
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!linux/devicetree/debug/dump-dts.sh
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linux/testvector-generation/genCheckpoint.gdb
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linux/testvector-generation/silencePipe
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linux/testvector-generation/silencePipe.control
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linux/testvector-generation/fixBinMem
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linux/testvector-generation/qemu-serial
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*.dtb
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synthDC/WORK
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synthDC/alib-52
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synthDC/*.log
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synthDC/*.svf
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synthDC/runs/
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synthDC/newRuns
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synthDC/ppa/PPAruns
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synthDC/ppa/plots
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synthDC/plots/
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synthDC/runArchive
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synthDC/hdl
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/pipelined/regression/power.saif
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tests/fp/vectors/*.tv
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# Temporary configs produced for synthesis
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pipelined/config/rv32e_FPUoff
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pipelined/config/rv32e_PMP0
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pipelined/config/rv32e_PMP16
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pipelined/config/rv32e_noMulDiv
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pipelined/config/rv32e_noPriv
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pipelined/config/rv32e_orig
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pipelined/config/rv32gc_FPUoff
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pipelined/config/rv32gc_PMP0
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pipelined/config/rv32gc_PMP16
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pipelined/config/rv32gc_noMulDiv
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pipelined/config/rv32gc_noPriv
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pipelined/config/rv32gc_orig
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pipelined/config/rv32ic_FPUoff
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pipelined/config/rv32ic_PMP0
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pipelined/config/rv32ic_PMP16
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pipelined/config/rv32ic_noMulDiv
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pipelined/config/rv32ic_noPriv
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pipelined/config/rv32ic_orig
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pipelined/config/rv64gc_FPUoff
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pipelined/config/rv64gc_PMP0
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pipelined/config/rv64gc_PMP16
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pipelined/config/rv64gc_noMulDiv
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pipelined/config/rv64gc_noPriv
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pipelined/config/rv64gc_orig
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pipelined/config/rv64ic_FPUoff
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pipelined/config/rv64ic_PMP0
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pipelined/config/rv64ic_PMP16
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pipelined/config/rv64ic_noMulDiv
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pipelined/config/rv64ic_noPriv
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pipelined/config/rv64ic_orig
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synthDC/Summary.csv
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pipelined/srt/exptestgen
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pipelined/srt/testgen
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pipelined/srt/qslc_r4a2
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pipelined/srt/qslc_r4a2.sv
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pipelined/srt/testvectors
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pipelined/regression/wkdir
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tests/custom/work
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tests/custom/*/*/*.list
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tests/custom/*/*/*.elf
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tests/custom/*/*/*.map
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tests/custom/*/*/*.memfile
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tests/custom/crt0/*.a
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/pipelined/regression/sd_model.log
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fpga/src/sdc/*
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fpga/src/sdc.tar.gz
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