DTowersM 1f4d56ba32 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)		2022-06-13 23:23:57 +00:00
..
common	Added WFI to the testbench instruction name decoder	2022-04-14 17:12:11 +00:00
fp	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
sdc	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
testbench-fp.sv	fma synth warnings and errors removed	2022-06-06 16:06:04 +00:00
testbench-fpga.sv	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00
testbench-linux.sv	Fixed recurrent issue with testbench where it would never stop	2022-06-03 18:56:24 -07:00
testbench.sv	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-06-07 23:58:58 +00:00
testbench.sv.bak	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
tests-fp.vh	fixed lint error	2022-05-28 10:20:13 -07:00
tests.vh	added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)	2022-06-13 23:23:57 +00:00