forked from Github_Repos/cvw
66 lines
3.2 KiB
Systemverilog
66 lines
3.2 KiB
Systemverilog
///////////////////////////////////////////
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// lrsc.sv
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//
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// Written: David_Harris@hmc.edu 17 July 2021
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// Modified:
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//
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// Purpose: Load Reserved / Store Conditional unit
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// Track the reservation and squash the store if it fails
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module lrsc
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(
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input logic clk, reset,
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input logic StallW,
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input logic MemReadM,
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input logic [1:0] PreLSURWM,
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output logic [1:0] LSURWM,
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input logic [1:0] LSUAtomicM,
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input logic [`PA_BITS-1:0] LSUPAdrM, // from mmu to dcache
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output logic SquashSCW
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);
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// Handle atomic load reserved / store conditional
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic lrM, scM, WriteAdrMatchM;
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logic SquashSCM;
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assign lrM = MemReadM & LSUAtomicM[0];
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assign scM = PreLSURWM[0] & LSUAtomicM[0];
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assign WriteAdrMatchM = PreLSURWM[0] & (LSUPAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
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assign SquashSCM = scM & ~WriteAdrMatchM;
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assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
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always_comb begin // ReservationValidM (next value of valid reservation)
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if (lrM) ReservationValidM = 1; // set valid on load reserve
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// if we implement multiple harts invalidate reservation if another hart stores to this reservation.
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else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
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else ReservationValidM = ReservationValidW; // otherwise don't change valid
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end
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flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, LSUPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
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flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
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endmodule
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