forked from Github_Repos/cvw
97 lines
4.8 KiB
Systemverilog
97 lines
4.8 KiB
Systemverilog
///////////////////////////////////////////
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// busfsm.sv
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//
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// Written: Ross Thompson ross1728@gmail.com December 29, 2021
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// Modified:
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//
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// Purpose: Load/Store Unit's interface to BUS for cacheless system
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module busfsm #(parameter integer LOGWPL)
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(input logic clk,
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input logic reset,
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input logic IgnoreRequest,
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input logic [1:0] RW,
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input logic BusAck,
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input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck.
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input logic CPUBusy,
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output logic BusStall,
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output logic BusWrite,
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output logic BusRead,
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output logic [1:0] HTRANS,
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output logic BusCommitted
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);
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typedef enum logic [2:0] {STATE_BUS_READY,
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STATE_BUS_UNCACHED_WRITE,
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STATE_BUS_UNCACHED_WRITE_DONE,
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STATE_BUS_UNCACHED_READ,
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STATE_BUS_UNCACHED_READ_DONE,
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STATE_BUS_CPU_BUSY} busstatetype;
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typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
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(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
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always_ff @(posedge clk)
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if (reset) BusCurrState <= #1 STATE_BUS_READY;
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else BusCurrState <= #1 BusNextState;
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always_comb begin
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case(BusCurrState)
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STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
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else if(RW[0]) BusNextState = STATE_BUS_UNCACHED_WRITE;
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else if(RW[1]) BusNextState = STATE_BUS_UNCACHED_READ;
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else BusNextState = STATE_BUS_READY;
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STATE_BUS_UNCACHED_WRITE: if(BusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
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else BusNextState = STATE_BUS_UNCACHED_WRITE;
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STATE_BUS_UNCACHED_READ: if(BusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE;
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else BusNextState = STATE_BUS_UNCACHED_READ;
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STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
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else BusNextState = STATE_BUS_READY;
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STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
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else BusNextState = STATE_BUS_READY;
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STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
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else BusNextState = STATE_BUS_READY;
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default: BusNextState = STATE_BUS_READY;
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endcase
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end
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assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) |
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(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
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(BusCurrState == STATE_BUS_UNCACHED_READ);
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assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0] & ~IgnoreRequest) |
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(BusCurrState == STATE_BUS_UNCACHED_WRITE);
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assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
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(BusCurrState == STATE_BUS_UNCACHED_READ);
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assign BusCommitted = BusCurrState != STATE_BUS_READY;
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assign HTRANS = (BusRead | BusWrite) & (~BusAck) ? AHB_NONSEQ : AHB_IDLE;
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endmodule
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