Ross Thompson 38adcb5b17 Minor simplification of cacheway way selection muxes.		2022-12-09 16:42:05 -06:00
..
cache	Minor simplification of cacheway way selection muxes.	2022-12-09 16:42:05 -06:00
ebu	Moved all remaining bus logic from the LSU into ahbcacheinterface.	2022-11-11 14:30:32 -06:00
fpu	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."	2022-12-04 00:01:58 +00:00
generic	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
hazard	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
ieu	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
ifu	Fixed bug Kip found.	2022-12-06 10:37:45 -06:00
lsu	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
mmu	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
muldiv	code cleanup	2022-12-01 08:15:48 -08:00
ppa
privileged	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
uncore
wally	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
sdc