forked from Github_Repos/cvw
88 lines
3.3 KiB
ArmAsm
88 lines
3.3 KiB
ArmAsm
///////////////////////////////////////////
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//
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// WALLY-uart-timeout
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@hmc.edu>
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//
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// Created 2022-10-24
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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RVTEST_ISA("RV32I")
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout)
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.equ UART, 0x10000000
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.equ UART_RBR, (UART)
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.equ UART_THR, (UART)
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.equ UART_IER, (UART+0x01)
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.equ UART_IIR, (UART+0x02)
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.equ UART_FCR, (UART+0x02)
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.equ UART_LCR, (UART+0x03)
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.equ UART_MCR, (UART+0x04)
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.equ UART_LSR, (UART+0x05)
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.equ UART_MSR, (UART+0x06)
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.equ UART_Scr, (UART+0x07)
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INIT_TESTS
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TRAP_HANDLER m
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WRITE08 UART_IER, 0x07 // enable data available, buffer empty, and line status interrupts
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WRITE08 UART_FCR, 0x81 // Set FIFO threshold to 8 and enable FIFO mode
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WRITE08 UART_LCR, 0x03 // set word transmit length to be 8 bits
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WRITE08 UART_THR, 0xA5 // write A5 to transmit register
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WRITE08 UART_THR, 0xA6 // write A6 to transmit register
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// since only 2/8 words have been written to the register, we should wait for a long time and get an interrupt
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li t2, 0x1000 // counter variable
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wait_for_timeout_loop:
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li t3, UART_IIR
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lb t4, 0(t3) // load the value out of interrupt ID register
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li t3, 0xCC // value for FIFO enabled and character timeout interrupt pending
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beq t3, t4, interrupt_success // If that interrupt is pending, we have succeeded in timing out
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// *** won't the processor also try to actually handle the interrupt?
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// Should I just let that happen? or is this a better option
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addi t2, t2, -1
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beqz t2, no_interrupt // at the end of the loop with not interrupts means this test failed.
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j wait_for_timeout_loop // continue loop
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no_interrupt:
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li t2, 0xbad // interrupt not taken. write bad value to the output
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sw t2, 0(t1)
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addi t1, t1, 4
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addi a6, a6, 4
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j end_of_section
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interrupt_success:
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li t2, 0x600d // interrupt successfully taken after some time. write good value to the output.
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sw t2, 0(t1)
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addi t1, t1, 4
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addi a6, a6, 4
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j end_of_section
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end_of_section: // end of this test
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END_TESTS
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TEST_STACK_AND_DATA
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