forked from Github_Repos/cvw
535 lines
25 KiB
Systemverilog
535 lines
25 KiB
Systemverilog
///////////////////////////////////////////
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// uart.sv
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//
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// Written: David_Harris@hmc.edu 21 January 2021
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// Modified:
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//
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// Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs
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// Emulates interface of Texas Instruments PC16550D
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// https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/PC16550D.pdf
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// Compatible with UART in Imperas Virtio model ***
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//
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// Compatible with most of PC16550D with the following known exceptions:
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// Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
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// Timeout not ye implemented***
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off UNOPTFLAT */
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module uartPC16550D(
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// Processor Interface
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input logic HCLK, HRESETn,
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input logic [2:0] A,
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input logic [7:0] Din,
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output logic [7:0] Dout,
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input logic MEMRb, MEMWb,
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output logic INTR, TXRDYb, RXRDYb,
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// Clocks
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output logic BAUDOUTb,
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input logic RCLK,
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// E1A Driver
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input logic SIN, DSRb, DCDb, CTSb, RIb,
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output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
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);
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// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
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typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
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// Registers
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logic [10:0] RBR;
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logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
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logic [3:0] IER, MSR;
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logic [4:0] MCR;
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// Syncrhonized and delayed UART signals
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logic SINd, DSRbd, DCDbd, CTSbd, RIbd;
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logic SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync;
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logic DSRb2, DCDb2, CTSb2, RIb2;
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logic SOUTbit;
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// Control signals
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logic loop; // loopback mode
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logic DLAB; // Divisor Latch Access Bit (LCR bit 7)
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// Baud and rx/tx timing
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logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
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logic [16+`UART_PRESCALE-1:0] baudcount;
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logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
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logic [3:0] rxbitsreceived, txbitssent;
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statetype rxstate, txstate;
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// shift registrs and FIFOs
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logic [9:0] rxshiftreg;
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logic [10:0] rxfifo[15:0];
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logic [7:0] txfifo[15:0];
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logic [4:0] rxfifotailunwrapped;
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logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
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logic [3:0] rxfifoentries, txfifoentries;
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logic [3:0] rxbitsexpected, txbitsexpected;
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// receive data
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logic [10:0] RXBR;
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logic [6:0] rxtimeoutcnt;
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logic rxcentered;
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logic rxparity, rxparitybit, rxstopbit;
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logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
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logic rxdataready;
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logic rxfifoempty, rxfifotriggered, rxfifotimeout;
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logic rxfifodmaready;
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logic [8:0] rxdata9;
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logic [7:0] rxdata;
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logic [15:0] RXerrbit, rxfullbit;
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logic [31:0] rxfullbitunwrapped;
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// transmit data
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logic [7:0] TXHR, nexttxdata;
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logic [11:0] txdata, txsr;
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logic txnextbit, txhrfull, txsrfull;
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logic txparity;
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logic txfifoempty, txfifofull, txfifodmaready;
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// control signals
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logic fifoenabled, fifodmamodesel, evenparitysel;
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// interrupts
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logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
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logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
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logic rxdataavailintr, modemstatusintr, intrpending;
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logic [2:0] intrID;
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logic baudpulseComb;
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///////////////////////////////////////////
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// Input synchronization: 2-stage synchronizer
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///////////////////////////////////////////
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always_ff @(posedge HCLK) begin
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{SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
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{SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} :
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{SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
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{DSRb2, DCDb2, CTSb2, RIb2} <= #1 {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes
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end
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///////////////////////////////////////////
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// Register interface (Table 1, note some are read only and some write only)
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///////////////////////////////////////////
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin // Table 3 Reset Configuration
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IER <= #1 4'b0;
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FCR <= #1 8'b0;
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if (`QEMU) LCR <= #1 8'b0; else LCR <= #1 8'b11; // fpga only **** BUG
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MCR <= #1 5'b0;
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LSR <= #1 8'b01100000;
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MSR <= #1 4'b0;
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if (`FPGA) begin
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DLL <= #1 8'd11;
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DLM <= #1 8'b0;
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end else begin
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DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
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DLM <= #1 8'b0;
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end
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/* -----\/----- EXCLUDED -----\/-----
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-----/\----- EXCLUDED -----/\----- */
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SCR <= #1 8'b0; // not strictly necessary to reset
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end else begin
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if (~MEMWb) begin
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case (A)
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/* -----\/----- EXCLUDED -----\/-----
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3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
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3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
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-----/\----- EXCLUDED -----/\----- */
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// *** BUG FIX ME for now for the divider to be 11. Our clock is 23 Mhz. 23Mhz /(25 * 16) = 57600 baud, which is close enough to 57600 baud
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3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
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3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
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3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
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3'b011: LCR <= #1 Din;
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3'b100: MCR <= #1 Din[4:0];
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3'b101: LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3
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3'b110: MSR <= #1 Din[3:0];
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3'b111: SCR <= #1 Din;
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endcase
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end
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// Line Status Register (8.6.3)
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// Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay.
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LSR[0] <= #1 rxdataready; // Data ready
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LSR[1] <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error
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LSR[2] <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error
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LSR[3] <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error
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LSR[4] <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator
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LSR[5] <= #1 THRE; // THRE
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LSR[6] <= #1 ~txsrfull & THRE; // TEMT
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if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error
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// Modem Status Register (8.6.8)
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MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
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MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready
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MSR[2] <= #1 MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator
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MSR[3] <= #1 MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect
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end
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always_comb
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if (~MEMRb)
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case (A)
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3'b000: if (DLAB) Dout = DLL; else Dout = RBR[7:0];
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3'b001: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]};
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3'b010: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register
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3'b011: Dout = LCR;
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3'b100: Dout = {3'b000, MCR};
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3'b101: Dout = LSR;
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3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]};
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3'b111: Dout = SCR;
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endcase
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else Dout = 8'b0;
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///////////////////////////////////////////
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// Baud rate generator
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// consider switching to same fixed-frequency reference clock used for TIME register
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// prescale by factor of 2^UART_PRESCALE to allow for high-frequency reference clock
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// Unlike PC16550D, this unit is hardwired with same rx and tx baud clock
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// *** add table of scale factors to get 16x uart clk
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///////////////////////////////////////////
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// Ross Thompson: Found a bug. If the baud rate dividers DLM, and DLL are reloaded
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// the baudcount is not reset to {DLM, DLL, UART_PRESCALE}
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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baudcount <= #1 1;
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baudpulse <= #1 0;
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end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin
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baudcount <= #1 1;
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end else begin
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// the baudpulse is too long by 2 clock cycles.
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// This is cause baudpulse is registered adding 1 cycle and
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// baudcount is reset when baudcount equals the threshold {DLM, DLL, UART_PRESCALE}
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// rather than 1 less than that value. Alternatively the reset value could be 1 rather
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// than 0.
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baudpulse <= #1 baudpulseComb;
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baudcount <= #1 baudpulseComb ? 1 : baudcount +1;
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end
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assign baudpulseComb = (baudcount == {DLM, DLL, {(`UART_PRESCALE){1'b0}}});
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assign txbaudpulse = baudpulse;
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assign BAUDOUTb = ~baudpulse;
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assign rxbaudpulse = ~RCLK; // usually BAUDOUTb tied to RCLK externally
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///////////////////////////////////////////
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// receive timing and control
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///////////////////////////////////////////
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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rxoversampledcnt <= #1 0;
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rxstate <= #1 UART_IDLE;
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rxbitsreceived <= #1 0;
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rxtimeoutcnt <= #1 0;
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end else begin
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if (rxstate == UART_IDLE & ~SINsync) begin // got start bit
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rxstate <= #1 UART_ACTIVE;
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rxoversampledcnt <= #1 0;
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rxbitsreceived <= #1 0;
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rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving
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end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin
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rxoversampledcnt <= #1 rxoversampledcnt + 1; // 16x oversampled counter
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if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1;
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if (rxbitsreceived == rxbitsexpected) rxstate <= #1 UART_DONE; // pulse rxdone for a cycle
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end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin
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if (rxbreak & ~SINsync) rxstate <= #1 UART_BREAK;
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else rxstate <= #1 UART_IDLE;
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end
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// timeout counting
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if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= #1 0; // reset timeout on read
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else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
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end
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// ***explain why
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if(`QEMU) assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE
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else assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
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assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit
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///////////////////////////////////////////
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// receive shift register, buffer register, FIFO
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///////////////////////////////////////////
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
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else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
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assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done
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assign rxstopbit = rxshiftreg[0];
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always_comb
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case(LCR[1:0]) // check how many bits used. Grab all bits including possible parity
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2'b00: rxdata9 = {3'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6]}; // 5-bit character
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2'b01: rxdata9 = {2'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7]}; // 6-bit
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2'b10: rxdata9 = {1'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8]}; // 7-bit
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2'b11: rxdata9 = { rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8], rxshiftreg[9]}; // 8-bit
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endcase
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assign rxdata = LCR[3] ? rxdata9[7:0] : rxdata9[8:1]; // discard parity bit
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// ERROR CONDITIONS
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assign rxparity = ^rxdata;
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assign rxparityerr = rxparity ^ rxparitybit ^ ~evenparitysel; // Check even/odd parity (*** check if LCR needs to be inverted)
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assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full
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assign rxframingerr = ~rxstopbit; // framing error if no stop bit
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assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
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// receive FIFO and register
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0;
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end else begin
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if (rxstate == UART_DONE) begin
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RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
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if (fifoenabled) begin
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rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
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rxfifohead <= #1 rxfifohead + 1;
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end
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rxdataready <= #1 1;
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end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo
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if (fifoenabled) begin
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if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1;
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if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
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end else begin
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rxdataready <= #1 0;
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RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
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end
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end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register
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if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents
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rxfifohead <= #1 0; rxfifotail <= #1 0;
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end
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end
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assign rxfifoempty = (rxfifohead == rxfifotail);
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// verilator lint_off WIDTH
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assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) :
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(rxfifohead + 16 - rxfifotail);
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// verilator lint_on WIDTH
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assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
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//assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet
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assign rxfifotimeout = 0; // disabled pending fix
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// detect any errors in rx fifo
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// although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
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// tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping
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assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail};
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genvar i;
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for (i=0; i<32; i++) begin:rxfull
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if (i == 0) assign rxfullbitunwrapped[i] = (rxfifohead==0) & (rxfifotail != 0);
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else assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i);
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end
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for (i=0; i<16; i++) begin:rx
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assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
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assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
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/* if (i > 0)
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assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
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else
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assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
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end
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assign rxfifohaserr = |(RXerrbit & rxfullbit);
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// receive buffer register and ready bit
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always_ff @(posedge HCLK, negedge HRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
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if (~HRESETn) rxfifodmaready <= #1 0;
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else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= #1 1;
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else if (rxfifoempty) rxfifodmaready <= #1 0;
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always_comb
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if (fifoenabled) begin
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if (rxfifoempty) RBR = 11'b0;
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else RBR = rxfifo[rxfifotail];
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if (fifodmamodesel) RXRDYb = ~rxfifodmaready;
|
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else RXRDYb = rxfifoempty;
|
|
end else begin
|
|
RBR = RXBR;
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|
RXRDYb = ~rxdataready;
|
|
end
|
|
|
|
///////////////////////////////////////////
|
|
// transmit timing and control
|
|
///////////////////////////////////////////
|
|
always_ff @(posedge HCLK, negedge HRESETn)
|
|
if (~HRESETn) begin
|
|
txoversampledcnt <= #1 0;
|
|
txstate <= #1 UART_IDLE;
|
|
txbitssent <= #1 0;
|
|
end else if ((txstate == UART_IDLE) & txsrfull) begin // start transmitting
|
|
txstate <= #1 UART_ACTIVE;
|
|
txoversampledcnt <= #1 1;
|
|
txbitssent <= #1 0;
|
|
end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin
|
|
txoversampledcnt <= #1 txoversampledcnt + 1;
|
|
if (txnextbit) begin // transmit at end of phase
|
|
txbitssent <= #1 txbitssent+1;
|
|
if (txbitssent == txbitsexpected) txstate <= #1 UART_DONE;
|
|
end
|
|
end else if (txstate == UART_DONE) begin
|
|
txstate <= #1 UART_IDLE;
|
|
end
|
|
|
|
assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
|
|
// *** explain; is this necessary?
|
|
if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE
|
|
else assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
|
|
|
|
///////////////////////////////////////////
|
|
// transmit holding register, shift register, FIFO
|
|
///////////////////////////////////////////
|
|
always_comb begin // compute value for parity and tx holding register
|
|
nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register
|
|
case (LCR[1:0]) // compute parity from appropriate number of bits
|
|
2'b00: txparity = ^nexttxdata[4:0] ^ ~evenparitysel; // *** check polarity
|
|
2'b01: txparity = ^nexttxdata[5:0] ^ ~evenparitysel;
|
|
2'b10: txparity = ^nexttxdata[6:0] ^ ~evenparitysel;
|
|
2'b11: txparity = ^nexttxdata[7:0] ^ ~evenparitysel;
|
|
endcase
|
|
case({LCR[3], LCR[1:0]}) // parity, data bits
|
|
// load up start bit (0), 5-8 data bits, 0-1 parity bits, 2 stop bits (only one sometimes used), padding
|
|
3'b000: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], 6'b111111}; // 5 data, no parity
|
|
3'b001: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], 5'b11111}; // 6 data, no parity
|
|
3'b010: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], 4'b1111}; // 7 data, no parity
|
|
3'b011: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], 3'b111}; // 8 data, no parity
|
|
3'b100: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], txparity, 5'b11111}; // 5 data, parity
|
|
3'b101: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], txparity, 4'b1111}; // 6 data, parity
|
|
3'b110: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], txparity, 3'b111}; // 7 data, parity
|
|
3'b111: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], txparity, 2'b11}; // 8 data, parity
|
|
endcase
|
|
end
|
|
|
|
// registers & FIFO
|
|
always_ff @(posedge HCLK, negedge HRESETn)
|
|
if (~HRESETn) begin
|
|
txfifohead <= #1 0; txfifotail <= #1 0; txhrfull <= #1 0; txsrfull <= #1 0; TXHR <= #1 0; txsr <= #1 12'hfff;
|
|
end else begin
|
|
if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo
|
|
if (fifoenabled) begin
|
|
txfifo[txfifohead] <= #1 Din;
|
|
txfifohead <= #1 txfifohead + 1;
|
|
end else begin
|
|
TXHR <= #1 Din;
|
|
txhrfull <= #1 1;
|
|
end
|
|
$write("%c",Din); // for testbench
|
|
end
|
|
if (txstate == UART_IDLE) begin // move data into tx shift register if available
|
|
if (fifoenabled) begin
|
|
if (~txfifoempty) begin
|
|
txsr <= #1 txdata;
|
|
txfifotail <= #1 txfifotail+1;
|
|
txsrfull <= #1 1;
|
|
end
|
|
end else if (txhrfull) begin
|
|
txsr <= #1 txdata;
|
|
txhrfull <= #1 0;
|
|
txsrfull <= #1 1;
|
|
end
|
|
end else if (txstate == UART_DONE) txsrfull <= #1 0; // done transmitting shift register
|
|
else if (txstate == UART_ACTIVE & txnextbit) txsr <= #1 {txsr[10:0], 1'b1}; // shift txhr
|
|
if (!MEMWb & A == 3'b010) // writes to FIFO control register
|
|
if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents
|
|
txfifohead <= #1 0; txfifotail <= #1 0;
|
|
end
|
|
end
|
|
|
|
assign txfifoempty = (txfifohead == txfifotail);
|
|
// verilator lint_off WIDTH
|
|
assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) :
|
|
(txfifohead + 16 - txfifotail);
|
|
// verilator lint_on WIDTH
|
|
assign txfifofull = (txfifoentries == 4'b1111);
|
|
|
|
// transmit buffer ready bit
|
|
always_ff @(posedge HCLK, negedge HRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
|
|
if (~HRESETn) txfifodmaready <= #1 0;
|
|
else if (txfifoempty) txfifodmaready <= #1 1;
|
|
else if (txfifofull) txfifodmaready <= #1 0;
|
|
|
|
always_comb
|
|
if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready;
|
|
else TXRDYb = ~THRE;
|
|
|
|
// Transmitter pin
|
|
assign SOUTbit = txsr[11]; // transmit most significant bit
|
|
assign SOUT = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break
|
|
|
|
///////////////////////////////////////////
|
|
// interrupts
|
|
///////////////////////////////////////////
|
|
assign RXerr = |LSR[4:1]; // LS interrupt if any of the flags are true
|
|
assign RXerrIP = RXerr & ~squashRXerrIP; // intr squashed upon reading LSR
|
|
assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready;
|
|
assign THRE = fifoenabled ? txfifoempty : ~txhrfull;
|
|
assign THRE_IP = THRE & ~squashTHRE_IP; // THRE_IP squashed upon reading IIR
|
|
assign modemstatusintr = |MSR[3:0]; // set interrupt when modem pins change
|
|
|
|
// IIR: interrupt priority (Table 5)
|
|
// set intrID based on highest priority pending interrupt source; otherwise, no interrupt is pending
|
|
always_comb begin
|
|
intrpending = 1;
|
|
if (RXerrIP & IER[2]) intrID = 3'b011;
|
|
else if (rxdataavailintr & IER[0]) intrID = 3'b010;
|
|
else if (rxfifotimeout & fifoenabled & IER[0]) intrID = 3'b110;
|
|
else if (THRE_IP & IER[1]) intrID = 3'b001;
|
|
else if (modemstatusintr & IER[3]) intrID = 3'b000;
|
|
else begin
|
|
intrID = 3'b000;
|
|
intrpending = 0;
|
|
end
|
|
end
|
|
always @(posedge HCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin
|
|
|
|
// Side effect of reading LSR is lowering overrun, parity, framing, break intr's
|
|
assign setSquashRXerrIP = ~MEMRb & (A==3'b101);
|
|
assign resetSquashRXerrIP = (rxstate == UART_DONE);
|
|
assign squashRXerrIP = (prevSquashRXerrIP | setSquashRXerrIP) & ~resetSquashRXerrIP;
|
|
flopr #(1) squashRXerrIPreg(HCLK, ~HRESETn, squashRXerrIP, prevSquashRXerrIP);
|
|
// Side effect of reading IIR is lowering THRE_IP if most significant intr
|
|
assign setSquashTHRE_IP = ~MEMRb & (A==3'b010) & (intrID==3'h1); // there's a 1-cycle delay on set squash so that THRE_IP doesn't change during the process of reading IIR (otherwise combinational loop)
|
|
assign resetSquashTHRE_IP = ~THRE;
|
|
assign squashTHRE_IP = prevSquashTHRE_IP & ~resetSquashTHRE_IP;
|
|
flopr #(1) squashTHRE_IPreg(HCLK, ~HRESETn, squashTHRE_IP | setSquashTHRE_IP, prevSquashTHRE_IP);
|
|
|
|
///////////////////////////////////////////
|
|
// modem control logic
|
|
///////////////////////////////////////////
|
|
|
|
assign loop = MCR[4];
|
|
assign DTRb = ~MCR[0] | loop; // disable modem signals in loopback mode
|
|
assign RTSb = ~MCR[1] | loop;
|
|
assign OUT1b = ~MCR[2] | loop;
|
|
assign OUT2b = ~MCR[3] | loop;
|
|
|
|
assign DLAB = LCR[7];
|
|
assign evenparitysel = LCR[4];
|
|
assign fifoenabled = FCR[0];
|
|
assign fifodmamodesel = FCR[3];
|
|
always_comb
|
|
case (FCR[7:6])
|
|
2'b00: rxfifotriggerlevel = 1;
|
|
2'b01: rxfifotriggerlevel = 4;
|
|
2'b10: rxfifotriggerlevel = 8;
|
|
2'b11: rxfifotriggerlevel = 14;
|
|
endcase
|
|
|
|
endmodule
|
|
|
|
/* verilator lint_on UNOPTFLAT */
|