Ross Thompson ac0f6ddb7b I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.		2022-11-16 15:38:37 -06:00
..
wallypipelinedcore.sv	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
wallypipelinedsoc.sv	FIxed wallypipelinedsoc merge conflict	2022-08-25 15:36:47 -07:00
wallypipelinedsocwrapper.v	Removed logic from Verilog wrapper.	2022-08-21 14:07:43 -05:00