cvw/pipelined/src/fma
2022-05-12 07:22:06 +00:00
..
baby_torture_rz.tv Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
baby_torture.tv Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
fma16_template.v Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
fma16_testgen.c Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
fma16.v FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
fma.do Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
lint-fma Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
Makefile Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
sim-fma Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
sim-fma-batch FMA project ready to start 2022-03-01 20:58:08 +00:00
synth Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
testbench.v Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
torture.tv Checked in torture.tv 2022-04-27 13:06:24 +00:00
torturegen.pl Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
wave.do filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00