forked from Github_Repos/cvw
77 lines
3.2 KiB
Systemverilog
77 lines
3.2 KiB
Systemverilog
///////////////////////////////////////////
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// wally-pipelinedsoc.sv
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//
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// Written: David_Harris@hmc.edu 6 November 2020
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// Modified:
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//
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// Purpose: System on chip including pipelined processor and memories
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// Full RV32/64IC instruction set
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//
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// Note: the CSRs do not support the following features
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//- Disabling portions of the instruction set with bits of the MISA register
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//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
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// As of January 2020, virtual memory is not yet supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module wallypipelinedsoc (
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input logic clk, reset,
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// AHB Lite Interface
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// inputs from external memory
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input logic [`AHBW-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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// outputs to external memory, shared with uncore memory
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// I/O Interface
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout
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);
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// to instruction memory *** remove later
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logic [`XLEN-1:0] PCF;
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// Uncore signals
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logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
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logic HREADY, HRESP;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM, SwIntM; // from CLINT
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logic ExtIntM; // from PLIC
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logic [2:0] HADDRD;
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logic [3:0] HSIZED;
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logic HWRITED;
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logic [15:0] rd2; // bogus, delete when real multicycle fetch works
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logic [31:0] InstrF;
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// instantiate processor and memories
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wallypipelinedhart hart(.*);
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imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
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uncore uncore(.HWDATAIN(HWDATA), .*);
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endmodule |