forked from Github_Repos/cvw
63 lines
1.8 KiB
Systemverilog
63 lines
1.8 KiB
Systemverilog
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`include "wally-config.vh"
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module fclassify (
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input logic [63:0] SrcXE,
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input logic FmtE, // 0-Single 1-Double
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output logic [63:0] ClassResE
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);
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logic [31:0] Single;
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logic [63:0] Double;
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logic Sgn;
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logic Inf, NaN, Zero, Norm, Denorm;
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logic PInf, QNaN, PZero, PNorm, PDenorm;
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logic NInf, SNaN, NZero, NNorm, NDenorm;
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logic MaxExp, ExpZero, ManZero, FirstBitFrac;
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// Single and Double precision layouts
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assign Single = SrcXE[63:32];
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assign Double = SrcXE;
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assign Sgn = SrcXE[63];
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// basic calculations for readabillity
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assign ExpZero = FmtE ? ~|Double[62:52] : ~|Single[30:23];
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assign MaxExp = FmtE ? &Double[62:52] : &Single[30:23];
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assign ManZero = FmtE ? ~|Double[51:0] : ~|Single[22:0];
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assign FirstBitFrac = FmtE ? Double[51] : Single[22];
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// determine the type of number
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assign NaN = MaxExp & ~ManZero;
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assign Inf = MaxExp & ManZero;
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assign Zero = ExpZero & ManZero;
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assign Denorm= ExpZero & ~ManZero;
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assign Norm = ~ExpZero;
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// determine the sub categories
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assign QNaN = FirstBitFrac&NaN;
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assign SNaN = ~FirstBitFrac&NaN;
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assign PInf = ~Sgn&Inf;
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assign NInf = Sgn&Inf;
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assign PNorm = ~Sgn&Norm;
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assign NNorm = Sgn&Norm;
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assign PDenorm = ~Sgn&Denorm;
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assign NDenorm = Sgn&Denorm;
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assign PZero = ~Sgn&Zero;
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assign NZero = Sgn&Zero;
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// determine sub category and combine into the result
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// bit 0 - -Inf
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// bit 1 - -Norm
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// bit 2 - -Denorm
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// bit 3 - -Zero
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// bit 4 - +Zero
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// bit 5 - +Denorm
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// bit 6 - +Norm
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// bit 7 - +Inf
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// bit 8 - signaling NaN
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// bit 9 - quiet NaN
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assign ClassResE = {{54{1'b0}}, QNaN, SNaN, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf};
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endmodule
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