forked from Github_Repos/cvw
d3be04b7de
cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled providing the new update dated rather than the correct older value.
51 lines
1.3 KiB
Plaintext
51 lines
1.3 KiB
Plaintext
# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work-buildroot] {
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vdel -all -lib work-buildroot
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}
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vlib work-buildroot
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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vsim workopt -suppress 8852,12070
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add log -r /*
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do linux-wave.do
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run 300 ms
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#-- Run the Simulation
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#run -all
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#do ./wave-dos/linux-waves.do
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#run 60 ms
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#run -all
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exec ./slack-notifier/slack-notifier.py
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##quit
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