Ross Thompson 2ae7b555be File name change for cachereplacement policy to cacheLRU		2022-11-20 22:35:02 -06:00
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cache	File name change for cachereplacement policy to cacheLRU	2022-11-20 22:35:02 -06:00
ebu	Moved all remaining bus logic from the LSU into ahbcacheinterface.	2022-11-11 14:30:32 -06:00
fpu	comment cleanup	2022-11-16 10:23:20 -08:00
generic	Missing a file. Last commit will fail.	2022-11-17 17:45:41 -06:00
hazard	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-13 12:25:22 -06:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
lsu	Renamed Flush to FlushStage in the cache.	2022-11-14 14:11:05 -06:00
mmu	Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.	2022-11-14 16:02:20 -06:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Moving interlockfsm changes to a temporary branch.	2022-10-19 15:08:23 -05:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00