forked from Github_Repos/cvw
58 lines
1.4 KiB
Systemverilog
58 lines
1.4 KiB
Systemverilog
// xz.sv
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// David_Harris@hmc.edu 30 January 2022
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// Demonstrate impact of x and z.
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// load with vsim xz.sv
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module testbench();
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logic [3:0] d0, d1, d2;
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logic s0, s1, s2;
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tri [3:0] y;
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distributedmux dut(.d0, .d1, .d2, .s0, .s1, .s2, .y);
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initial begin
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d0 = 4'b0000; d1 = 4'b0101; // d2 unknown (xxxx)
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s0 = 0; s1 = 0; s2 = 0;
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#10; // y should be floating
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s0 = 1;
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#10; //y should be driven to 0000
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s0 = 0; s1 = 1;
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#10; // y should be driven to 0101
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s0 = 1;
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#10; // y should be driven to 0x0x because of contention on bits 0 and 2
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s0 = 0; s1 = 0; s2 = 1;
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#10; // y should be driven to unknown because d2 is unknown
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end
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endmodule
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module tristate #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a,
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input logic en,
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output logic [WIDTH-1:0] y);
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assign y = en ? a : 'z;
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endmodule
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module distributedmux(
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input logic [3:0] d0, d1, d2,
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input logic s0, s1, s2,
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output tri [3:0] y);
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tristate #(4) t0(d0, s0, y);
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tristate #(4) t1(d1, s1, y);
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tristate #(4) t2(d2, s2, y);
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endmodule
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module gpio #(parameter WIDTH=16) (
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input logic [WIDTH-1:0] GPIOOutVal, GPIOEn,
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output logic [WIDTH-1:0] GPIOInVal,
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inout tri [WIDTH-1:0] GPIOPin);
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assign GPIOInVal = GPIOPin;
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tristate #(1) ts[WIDTH-1:0](GPIOOutVal, GPIOEn, GPIOPin);
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endmodule
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module silly(output logic [128:0] y);
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assign y = 'bz;
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endmodule |