Jarred Allen 2a29def21c Add icache's read request to ahb wavs		2021-03-18 18:52:03 -04:00
..
wave-dos	Add icache's read request to ahb wavs	2021-03-18 18:52:03 -04:00
regression-wally.py	Undo accidental change	2021-03-16 18:16:00 -04:00
sim-busybear	busybear: add sim-busybear and sim-busybear-batch based on sim-wally	2021-03-01 21:01:15 +00:00
sim-busybear-batch	busybear: make a second .do file with better optimization for command line mode	2021-03-08 19:35:00 +00:00
sim-wally	Added test configurations	2021-01-25 11:28:43 -05:00
sim-wally-batch	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
sim-wally-rv32ic	maybe AHB works now	2021-03-18 17:47:00 -04:00
wally-busybear-batch.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-busybear.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-coremark_bare.do	fix to last commit	2021-03-17 15:07:02 -05:00
wally-coremark.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-peripherals-signals.do	refactored sim file	2021-03-05 14:25:16 -05:00
wally-peripherals.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-pipelined-batch.do	Condense the parallel and non-parallel wally-pipelined-batch.do files into one	2021-03-16 18:15:13 -04:00
wally-pipelined-ross.do	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
wally-pipelined.do	maybe AHB works now	2021-03-18 17:47:00 -04:00
wave-all.do	Added FlushF to hazard unit.	2021-02-19 16:36:51 -06:00
wave.do	Added possibly working OSU test bench as a precursor to running a bp benchmark.	2021-03-17 11:06:32 -05:00