forked from Github_Repos/cvw
57 lines
2.2 KiB
Systemverilog
57 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified: James Stine
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//
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// Purpose: 3-port output register file
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fregfile (
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input logic clk, reset,
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input logic we4,
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input logic [4:0] a1, a2, a3, a4,
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input logic [`FLEN-1:0] wd4,
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output logic [`FLEN-1:0] rd1, rd2, rd3);
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logic [`FLEN-1:0] rf[31:0];
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integer i;
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// three ported register file
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// read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
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// write fourth port on rising edge of clock (A4/WD4/WE4)
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// write occurs on falling edge of clock
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always_ff @(negedge clk) // or posedge reset)
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if (reset) for(i=0; i<32; i++) rf[i] <= 0;
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else if (we4) rf[a4] <= wd4;
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assign #2 rd1 = rf[a1];
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assign #2 rd2 = rf[a2];
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assign #2 rd3 = rf[a3];
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endmodule // regfile
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