forked from Github_Repos/cvw
43 lines
2.1 KiB
Systemverilog
43 lines
2.1 KiB
Systemverilog
`include "wally-config.vh"
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module divshiftcalc(
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input logic [`DIVb-(`RADIX/4):0] DivQm,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic [`DURLEN-1:0] DivEarlyTermShift,
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input logic [`NE+1:0] DivQe,
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output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
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output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
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output logic DivResDenorm,
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output logic [`NE+1:0] DivDenormShift
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);
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logic [`NE+1:0] NormShift;
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// is the result denromalized
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// if the exponent is 1 then the result needs to be normalized then the result is denormalizes
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assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
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// if the result is denormalized
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// 00000000x.xxxxxx... Exp = DivQe
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// .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1
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// .00xxxxxxxxxxxxx... << DivQe+NF+1 Exp = +1
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// .0000xxxxxxxxxxx... >> 1 Exp = 1
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// Left shift amount = DivQe+NF+1-1
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assign DivDenormShift = (`NE+2)'(`NF)+DivQe;
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// if the result is normalized
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// 00000000x.xxxxxx... Exp = DivQe
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// .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1
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// 00000000.xxxxxxx... << NF Exp = DivQe+1
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// 00000000x.xxxxxx... << NF Exp = DivQe (extra shift done afterwards)
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// 00000000xx.xxxxx... << 1? Exp = DivQe-1 (determined after)
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// inital Left shift amount = NF
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// shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
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assign NormShift = (`NE+2)'(`NF);
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// if the shift amount is negitive then dont shift (keep sticky bit)
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// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
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assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
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assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
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endmodule
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