James E. Stine 15d38f8c7f Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines ... Katherine/James		2021-12-29 12:59:17 -06:00
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BTBPredictor.txt	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
twoBitPredictor.txt	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
wally-config.vh	Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines	2021-12-29 12:59:17 -06:00