Katherine Parry db95151d8d fpu imperas tests run		2021-05-01 02:18:01 +00:00
..
csr.sv	fix to pcm bug	2021-04-29 15:21:08 -04:00
csrc.sv	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
csri.sv	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
csrm.sv	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00
csrn.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
csrs.sv	Merge branch 'tests' into icache-almost-working	2021-04-25 21:25:36 -05:00
csrsr.sv	Implement virtual memory protection	2021-04-21 19:58:36 -04:00
csru.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
privdec.sv	fpu imperas tests run	2021-05-01 02:18:01 +00:00
privileged.sv	fpu imperas tests run	2021-05-01 02:18:01 +00:00
trap.sv	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00