forked from Github_Repos/cvw
157 lines
3.8 KiB
ArmAsm
157 lines
3.8 KiB
ArmAsm
// -----------
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// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
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// version : 0.5.1
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// timestamp : Mon Aug 2 08:58:53 2021 GMT
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// usage : riscv_ctg \
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// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
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// --base-isa rv32e \
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// --randomize
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the lh instruction of the RISC-V E extension for the lh-align covergroup.
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//
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#define RVTEST_E
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32E")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lh-align)
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RVTEST_SIGBASE( x4,signature_x4_1)
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inst_0:
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// rs1 != rd, rs1==x3, rd==x2, ea_align == 0 and (imm_val % 4) == 0, imm_val == 0
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// opcode:lh op1:x3; dest:x2; immval:0x0; align:0
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TEST_LOAD(x4,x5,0,x3,x2,0x0,0,lh,0)
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inst_1:
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// rs1 == rd, rs1==x15, rd==x15, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
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// opcode:lh op1:x15; dest:x15; immval:0x5; align:0
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TEST_LOAD(x4,x5,0,x15,x15,0x5,4,lh,0)
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inst_2:
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// rs1==x12, rd==x14, ea_align == 0 and (imm_val % 4) == 2, imm_val < 0
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// opcode:lh op1:x12; dest:x14; immval:-0x556; align:0
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TEST_LOAD(x4,x5,0,x12,x14,-0x556,8,lh,0)
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inst_3:
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// rs1==x14, rd==x8, ea_align == 0 and (imm_val % 4) == 3,
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// opcode:lh op1:x14; dest:x8; immval:0x3ff; align:0
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TEST_LOAD(x4,x5,0,x14,x8,0x3ff,12,lh,0)
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inst_4:
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// rs1==x10, rd==x3, ea_align == 2 and (imm_val % 4) == 0,
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// opcode:lh op1:x10; dest:x3; immval:-0x8; align:2
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TEST_LOAD(x4,x5,0,x10,x3,-0x8,16,lh,2)
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inst_5:
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// rs1==x6, rd==x1, ea_align == 2 and (imm_val % 4) == 1,
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// opcode:lh op1:x6; dest:x1; immval:0x555; align:2
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TEST_LOAD(x4,x5,0,x6,x1,0x555,20,lh,2)
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inst_6:
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// rs1==x13, rd==x6, ea_align == 2 and (imm_val % 4) == 2,
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// opcode:lh op1:x13; dest:x6; immval:-0x6; align:2
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TEST_LOAD(x4,x5,0,x13,x6,-0x6,24,lh,2)
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inst_7:
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// rs1==x1, rd==x9, ea_align == 2 and (imm_val % 4) == 3,
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// opcode:lh op1:x1; dest:x9; immval:0x7ff; align:2
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TEST_LOAD(x4,x5,0,x1,x9,0x7ff,28,lh,2)
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inst_8:
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// rs1==x9, rd==x0,
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// opcode:lh op1:x9; dest:x0; immval:-0x800; align:0
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TEST_LOAD(x4,x3,0,x9,x0,-0x800,32,lh,0)
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inst_9:
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// rs1==x5, rd==x12,
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// opcode:lh op1:x5; dest:x12; immval:-0x800; align:0
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TEST_LOAD(x4,x3,0,x5,x12,-0x800,36,lh,0)
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RVTEST_SIGBASE( x1,signature_x1_0)
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inst_10:
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// rs1==x8, rd==x11,
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// opcode:lh op1:x8; dest:x11; immval:-0x800; align:0
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TEST_LOAD(x1,x3,0,x8,x11,-0x800,0,lh,0)
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inst_11:
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// rs1==x11, rd==x4,
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// opcode:lh op1:x11; dest:x4; immval:-0x800; align:0
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TEST_LOAD(x1,x3,0,x11,x4,-0x800,4,lh,0)
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inst_12:
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// rs1==x2, rd==x7,
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// opcode:lh op1:x2; dest:x7; immval:-0x800; align:0
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TEST_LOAD(x1,x3,0,x2,x7,-0x800,8,lh,0)
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inst_13:
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// rs1==x4, rd==x10,
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// opcode:lh op1:x4; dest:x10; immval:-0x800; align:0
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TEST_LOAD(x1,x3,0,x4,x10,-0x800,12,lh,0)
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inst_14:
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// rs1==x7, rd==x5,
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// opcode:lh op1:x7; dest:x5; immval:-0x800; align:0
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TEST_LOAD(x1,x3,0,x7,x5,-0x800,16,lh,0)
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inst_15:
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// rd==x13,
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// opcode:lh op1:x12; dest:x13; immval:-0x800; align:0
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TEST_LOAD(x1,x3,0,x12,x13,-0x800,20,lh,0)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x4_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x4_1:
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.fill 10*(XLEN/32),4,0xdeadbeef
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signature_x1_0:
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.fill 6*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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