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Configurable RISC-V Processor
56 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
206747b8b2
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Noah Boorstin 206747b8b2 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
riscv-o3@a13ac64fa5 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Busybear test now processes first 100 instrs correctly! 2021-01-28 01:19:27 -05:00
.gitignore Busybear test now processes first 100 instrs correctly! 2021-01-28 01:19:27 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor