forked from Github_Repos/cvw
64 lines
3.6 KiB
Systemverilog
64 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: unpack all inputs
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module unpack (
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input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
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input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
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input logic XEn, YEn, ZEn,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
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output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
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output logic XDenorm, ZDenorm, // is XYZ denormalized
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output logic XZero, YZero, ZZero, // is XYZ zero
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax // does X have the maximum exponent (NaN or Inf)
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);
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logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero
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logic XFracZero, YFracZero, ZFracZero; // is the fraction zero
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logic YExpMax, ZExpMax; // is the exponent all 1s
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unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
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.NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
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.Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero));
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unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
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.NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
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.Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero));
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unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
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.NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
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.Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
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// is the input denormalized
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assign XDenorm = ~XExpNonZero & ~XFracZero;
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assign ZDenorm = ~ZExpNonZero & ~ZFracZero;
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endmodule |