forked from Github_Repos/cvw
76 lines
3.9 KiB
Systemverilog
76 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA significand adder
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fmaadd(
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input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
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input logic [2*`NF+1:0] Pm, // the product's mantissa
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input logic Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
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input logic InvA, // invert the aligned addend
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input logic KillProd, // should the product be set to 0
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input logic ZmSticky,
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input logic [`NE-1:0] Ze,
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input logic [`NE+1:0] Pe,
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output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted
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output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
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output logic NegSum, // was the sum negitive
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output logic Ss,
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output logic [`NE+1:0] Se,
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output logic [3*`NF+5:0] Sm // the positive sum
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);
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logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum
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///////////////////////////////////////////////////////////////////////////////
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// Addition
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///////////////////////////////////////////////////////////////////////////////
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// Choose an inverted or non-inverted addend. Put carry into adder/LZA for addition
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assign AmInv = InvA ? ~Am : Am;
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// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
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assign PmKilled = KillProd ? '0 : Pm;
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// Do the addition
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// - calculate a positive and negitive sum in parallel
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// Zsticky Psticky
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// PreSum -1 = don't add 1 +1 = add 2
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// NegPreSum +1 = add 2 -1 = don't add 1
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// for NegPreSum the product is set to -1 whenever the product is killed, therefore add 1, 2 or 0
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assign {NegSum, PreSum} = {{`NF+3{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + {InvA, AmInv} + {{3*`NF+6{1'b0}}, InvA&~((ZmSticky&~KillProd))};
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assign NegPreSum = Am + {{`NF+2{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+4)'(0), ZmSticky&~KillProd, ~(ZmSticky)};
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum : PreSum;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign Ss = NegSum^Ps;
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assign Se = KillProd ? {2'b0, Ze} : Pe;
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endmodule
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