forked from Github_Repos/cvw
36 lines
2.3 KiB
Systemverilog
36 lines
2.3 KiB
Systemverilog
`include "wally-config.vh"
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module unpack (
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input logic [`FLEN-1:0] X, Y, Z, // inputs from register file
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input logic [`FPSIZES/3:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half
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output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ
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output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision)
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output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN
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output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN
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output logic XDenormE, ZDenormE, // is XYZ denormalized
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output logic XZeroE, YZeroE, ZZeroE, // is XYZ zero
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output logic XInfE, YInfE, ZInfE, // is XYZ infinity
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output logic XExpMaxE // does X have the maximum exponent (NaN or Inf)
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);
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logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ
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logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero
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logic XFracZero, YFracZero, ZFracZero; // is the fraction zero
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logic YExpMaxE, ZExpMaxE; // is the exponent all 1s
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unpackinput unpackinputX (.In(X), .FmtE, .Sgn(XSgnE), .Exp(XExpE), .Man(XManE),
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.NaN(XNaNE), .SNaN(XSNaNE), .ExpNonZero(XExpNonZero),
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.Zero(XZeroE), .Inf(XInfE), .ExpMax(XExpMaxE), .FracZero(XFracZero));
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unpackinput unpackinputY (.In(Y), .FmtE, .Sgn(YSgnE), .Exp(YExpE), .Man(YManE),
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.NaN(YNaNE), .SNaN(YSNaNE), .ExpNonZero(YExpNonZero),
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.Zero(YZeroE), .Inf(YInfE), .ExpMax(YExpMaxE), .FracZero(YFracZero));
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unpackinput unpackinputZ (.In(Z), .FmtE, .Sgn(ZSgnE), .Exp(ZExpE), .Man(ZManE),
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.NaN(ZNaNE), .SNaN(ZSNaNE), .ExpNonZero(ZExpNonZero),
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.Zero(ZZeroE), .Inf(ZInfE), .ExpMax(ZExpMaxE), .FracZero(ZFracZero));
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// is the input denormalized
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assign XDenormE = ~XExpNonZero & ~XFracZero;
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assign ZDenormE = ~ZExpNonZero & ~ZFracZero;
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endmodule |