forked from Github_Repos/cvw
136 lines
4.9 KiB
Systemverilog
136 lines
4.9 KiB
Systemverilog
///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module srtpreproc (
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input logic clk,
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input logic DivStart,
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input logic [`NF:0] Xm, Ym,
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input logic [`NE-1:0] Xe, Ye,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic XZero,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb:0] X,
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output logic [`DIVN-2:0] Dpreproc,
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output logic [`DURLEN-1:0] Dur
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);
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// logic [`XLEN-1:0] PosA, PosB;
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// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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logic [`NF-1:0] PreprocA, PreprocX;
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logic [`NF-1:0] PreprocB, PreprocY;
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logic [`NF+1:0] SqrtX;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [`NE+1:0] Qe;
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// assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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// assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
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// lzc #(`XLEN) lzcA (PosA, zeroCntA);
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// lzc #(`XLEN) lzcB (PosB, zeroCntB);
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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lzc #(`NF+1) lzcX (Xm, XZeroCnt);
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lzc #(`NF+1) lzcY (Ym, YZeroCnt);
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// assign ExtraA = {PosA, {`DIVLEN-`XLEN{1'b0}}};
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// assign ExtraB = {PosB, {`DIVLEN-`XLEN{1'b0}}};
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// assign PreprocA = ExtraA << zeroCntA;
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// assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = Xm[`NF-1:0]<<XZeroCnt;
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assign PreprocY = Ym[`NF-1:0]<<YZeroCnt;
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assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
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assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
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assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
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assign Dur = (`DURLEN)'(`FPDUR);
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// radix 2 radix 4
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// 1 copies DIVLEN+2 DIVLEN+2/2
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// 2 copies DIVLEN+2/2 DIVLEN+2/2*2
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// 4 copies DIVLEN+2/4 DIVLEN+2/2*4
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// 8 copies DIVLEN+2/8 DIVLEN+2/2*8
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// DIVRESLEN = DIVLEN or DIVLEN+2
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// r = 1 or 2
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// DIVRESLEN/(r*`DIVCOPIES)
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flopen #(`NE+2) expflop(clk, DivStart, Qe, QeM);
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expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .XZeroCnt, .YZeroCnt, .Qe);
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endmodule
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module expcalc(
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input logic [`FMTBITS-1:0] Fmt,
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input logic [`NE-1:0] Xe, Ye,
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input logic Sqrt,
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input logic XZero,
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input logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt,
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output logic [`NE+1:0] Qe
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);
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logic [`NE-2:0] Bias;
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logic [`NE+1:0] SXExp;
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logic [`NE+1:0] SExp;
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logic [`NE+1:0] DExp;
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if (`FPSIZES == 1) begin
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assign Bias = (`NE-1)'(`BIAS);
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end else if (`FPSIZES == 2) begin
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assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
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end else if (`FPSIZES == 3) begin
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always_comb
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case (Fmt)
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`FMT: Bias = (`NE-1)'(`BIAS);
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`FMT1: Bias = (`NE-1)'(`BIAS1);
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`FMT2: Bias = (`NE-1)'(`BIAS2);
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default: Bias = 'x;
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endcase
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end else if (`FPSIZES == 4) begin
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always_comb
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case (Fmt)
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2'h3: Bias = (`NE-1)'(`Q_BIAS);
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2'h1: Bias = (`NE-1)'(`D_BIAS);
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2'h0: Bias = (`NE-1)'(`S_BIAS);
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2'h2: Bias = (`NE-1)'(`H_BIAS);
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endcase
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end
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assign SXExp = {2'b0, Xe} - {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, XZeroCnt} - (`NE+1)'(`BIAS);
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assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
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// correct exponent for denormalized input's normalization shifts
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assign DExp = ({2'b0, Xe} - {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, XZeroCnt} - {2'b0, Ye} + {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, YZeroCnt} + {3'b0, Bias})&{`NE+2{~XZero}};
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assign Qe = Sqrt ? SExp : DExp;
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endmodule |