forked from Github_Repos/cvw
60 lines
1016 B
Systemverilog
Executable File
60 lines
1016 B
Systemverilog
Executable File
//
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// File name : tb
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// Title : test
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// project : HW3
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// Library : test
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// Purpose : definition of modules for testbench
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// notes :
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//
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// Copyright Oklahoma State University
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//
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// Top level stimulus module
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`timescale 1ns/1ps
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module stimulus;
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logic [7:0] B;
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logic [2:0] ZP;
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logic ZV;
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logic clk;
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integer handle3;
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integer desc3;
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integer i;
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// instatiate part to test
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lzd_hier #(8) dut (B, ZP, ZV);
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initial
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begin
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clk = 1'b1;
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forever #5 clk = ~clk;
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end
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initial
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begin
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handle3 = $fopen("lzd.out");
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desc3 = handle3;
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end
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initial
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begin
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for (i=0; i < 256; i=i+1)
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begin
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// Put vectors before beginning of clk
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@(posedge clk)
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begin
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B = $random;
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end
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@(negedge clk)
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begin
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$fdisplay(desc3, "%b || %b %b", B, ZP, ZV);
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end
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end // for (i=0; i < 256; i=i+1)
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$finish;//
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end // initial begin
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endmodule // stimulus
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