forked from Github_Repos/cvw
219 lines
8.4 KiB
Systemverilog
219 lines
8.4 KiB
Systemverilog
///////////////////////////////////////////
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// uncore.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified: Ben Bracker 6 Mar 2021 to better fit AMBA 3 AHB-Lite spec
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//
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// Purpose: System-on-Chip components outside the core (hart)
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// Memories, peripherals, external bus control
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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// *** need idiom to map onto cache RAM with byte writes
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// *** and use memread signal to reduce power when reads aren't needed
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module uncore (
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// AHB Bus Interface
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input logic HCLK, HRESETn,
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input logic [31:0] HADDR,
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input logic [`AHBW-1:0] HWDATAIN,
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input logic HWRITE,
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input logic [2:0] HSIZE,
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input logic [2:0] HBURST,
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input logic [3:0] HPROT,
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input logic [1:0] HTRANS,
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input logic HMASTLOCK,
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input logic [`AHBW-1:0] HRDATAEXT,
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input logic HREADYEXT, HRESPEXT,
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output logic [`AHBW-1:0] HRDATA,
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output logic HREADY, HRESP,
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output logic HSELEXT,
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// delayed signals
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input logic [2:0] HADDRD,
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input logic [3:0] HSIZED,
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input logic HWRITED,
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// peripheral pins
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output logic TimerIntM, SwIntM, ExtIntM,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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input logic UARTSin,
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output logic UARTSout,
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output logic SDCCmdOut,
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output logic SDCCmdOE,
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input logic SDCCmdIn,
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input logic [3:0] SDCDatIn,
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output logic SDCCLK,
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output logic [63:0] MTIME_CLINT, MTIMECMP_CLINT
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);
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logic [`XLEN-1:0] HWDATA;
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logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC;
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logic [8:0] HSELRegions;
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logic HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
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logic HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
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logic HRESPRam, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART, HRESPSDC;
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logic HREADYRam, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART, HRESPSDCD;
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logic [`XLEN-1:0] HREADBootRom;
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logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
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logic HSELNoneD;
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logic UARTIntr,GPIOIntr;
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logic SDCIntM;
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// Determine which region of physical memory (if any) is being accessed
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// Use a trimmed down portion of the PMA checker - only the address decoders
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// Set access types to all 1 as don't cares because the MMU has already done access checking
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adrdecs adrdecs({{(`PA_BITS-32){1'b0}}, HADDR}, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
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// unswizzle HSEL signals
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assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
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// subword accesses: converts HWDATAIN to HWDATA
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subwordwrite sww(
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.HRDATA,
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.HADDRD, .HSIZED,
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.HWDATAIN, .HWDATA);
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generate
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// on-chip RAM outside hart
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if (`RAM_SUPPORTED) begin : ram
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ram #(
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.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.HCLK, .HRESETn,
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.HSELRam, .HADDR,
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.HWRITE, .HREADY,
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.HTRANS, .HWDATA, .HREADRam,
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.HRESPRam, .HREADYRam);
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end
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if (`BOOTROM_SUPPORTED) begin : bootrom
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ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
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bootrom(
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.HCLK, .HRESETn,
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.HSELRam(HSELBootRom), .HADDR,
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.HWRITE, .HREADY, .HTRANS,
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.HWDATA,
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.HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
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end
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// memory-mapped I/O peripherals
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if (`CLINT_SUPPORTED == 1) begin : clint
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clint clint(
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.HCLK, .HRESETn,
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.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
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.HWDATA, .HREADY, .HTRANS,
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.HREADCLINT,
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.HRESPCLINT, .HREADYCLINT,
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.MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT),
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.TimerIntM, .SwIntM);
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end else begin : clint
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assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
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assign TimerIntM = 0; assign SwIntM = 0;
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end
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if (`PLIC_SUPPORTED == 1) begin : plic
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plic plic(
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.HCLK, .HRESETn,
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.HSELPLIC, .HADDR(HADDR[27:0]),
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.HWRITE, .HREADY, .HTRANS, .HWDATA,
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.UARTIntr, .GPIOIntr,
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.HREADPLIC, .HRESPPLIC, .HREADYPLIC,
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.ExtIntM);
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end else begin : plic
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assign ExtIntM = 0;
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end
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if (`GPIO_SUPPORTED == 1) begin : gpio
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gpio gpio(
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.HCLK, .HRESETn, .HSELGPIO,
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.HADDR(HADDR[7:0]),
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.HWDATA,
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.HWRITE, .HREADY,
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.HTRANS,
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.HREADGPIO,
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.HRESPGPIO, .HREADYGPIO,
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.GPIOPinsIn,
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.GPIOPinsOut, .GPIOPinsEn,
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.GPIOIntr);
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end else begin : gpio
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assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
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end
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if (`UART_SUPPORTED == 1) begin : uart
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uart uart(
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.HCLK, .HRESETn,
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.HSELUART,
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.HADDR(HADDR[2:0]),
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.HWRITE, .HWDATA,
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.HREADUART, .HRESPUART, .HREADYUART,
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.SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
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.SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface
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.OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU
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end else begin : uart
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assign UARTSout = 0; assign UARTIntr = 0;
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end
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if (`SDC_SUPPORTED == 1) begin : sdc
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SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
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.HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
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// sdc interface
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.SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
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// interrupt to PLIC
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.SDCIntM
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);
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end else begin : sdc
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assign SDCCLK = 0;
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assign SDCCmdOut = 0;
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assign SDCCmdOE = 0;
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end
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endgenerate
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// mux could also include external memory
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// AHB Read Multiplexer
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assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
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({`XLEN{HSELEXTD}} & HRDATAEXT) |
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({`XLEN{HSELCLINTD}} & HREADCLINT) |
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({`XLEN{HSELPLICD}} & HREADPLIC) |
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({`XLEN{HSELGPIOD}} & HREADGPIO) |
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({`XLEN{HSELBootRomD}} & HREADBootRom) |
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({`XLEN{HSELUARTD}} & HREADUART) |
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({`XLEN{HSELSDCD}} & HREADSDC);
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assign HRESP = HSELRamD & HRESPRam |
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HSELEXTD & HRESPEXT |
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HSELCLINTD & HRESPCLINT |
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HSELPLICD & HRESPPLIC |
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HSELGPIOD & HRESPGPIO |
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HSELBootRomD & HRESPBootRom |
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HSELUARTD & HRESPUART |
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HSELSDC & HRESPSDC;
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assign HREADY = HSELRamD & HREADYRam |
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HSELEXTD & HREADYEXT |
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HSELCLINTD & HREADYCLINT |
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HSELPLICD & HREADYPLIC |
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HSELGPIOD & HREADYGPIO |
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HSELBootRomD & HREADYBootRom |
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HSELUARTD & HREADYUART |
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HSELSDCD & HREADYSDC |
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HSELNoneD; // don't lock up the bus if no region is being accessed
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// Address Decoder Delay (figure 4-2 in spec)
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flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
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endmodule
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