cvw/src/fpu
2023-02-21 09:57:57 -08:00
..
fdivsqrt Disabled W64M register for RV32 2023-02-19 07:03:31 -08:00
fma Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
postproc Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
fclassify.sv Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
fcmp.sv Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
fctrl.sv Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well. 2023-02-21 09:32:17 -08:00
fcvt.sv Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
fhazard.sv Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
fpu.sv Fixed Issue #65 fmv sign selection. Sign needs to come from most significant bit of raw X source without doing NaN Box fixes first. 2023-02-21 09:57:57 -08:00
fregfile.sv Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
fsgninj.sv Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
unpack.sv Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55 2023-02-17 20:51:43 -08:00
unpackinput.sv Fixed issue #57 of sign selection for improperly NaN-boxed number 2023-02-18 05:34:40 -08:00