forked from Github_Repos/cvw
1ea3e8120a
- top module includes exponent module now Notes: - may be a better implementation of the exponent module rather than having what I believe are two adders currently
290 lines
8.6 KiB
Systemverilog
290 lines
8.6 KiB
Systemverilog
///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu 13 January 2022
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// Modified:
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module srt #(parameter Nf=52) (
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input logic clk,
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input logic Start,
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input logic Stall, // *** multiple pipe stages
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input logic Flush, // *** multiple pipe stages
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// Floating Point Inputs
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// later add exponents, signs, special cases
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input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits
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// end of floating point inputs
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input logic [Nf-1:0] SrcXFrac, SrcYFrac,
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputss
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input logic Sqrt, // perform square root, not divide
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output logic [Nf-1:0] Quot, Rem, // *** later handle integers
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output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision
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output logic [3:0] Flags
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);
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logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [Nf-1:0] X, Dpreproc;
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logic [Nf+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [Nf+2:0] rp, rm;
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srtpreproc #(Nf) preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc);
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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mux2 #(Nf+4) wsmux({WSA[54:0], 1'b0}, {4'b0001, X}, Start, WSN);
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flop #(Nf+4) wsflop(clk, WSN, WS);
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mux2 #(Nf+4) wcmux({WCA[54:0], 1'b0}, 56'b0, Start, WCN);
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flop #(Nf+4) wcflop(clk, WCN, WC);
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flopen #(Nf+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// Accumulate quotient digits in a shift register
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qsel #(Nf) qsel(WS[55:52], WC[55:52], qp, qz, qm);
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qacc #(Nf+3) qacc(clk, Start, qp, qz, qm, rp, rm);
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// Divisor Selection logic
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inv dinv(D, Db);
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mux3onehot divisorsel(Db, 56'b0, D, qp, qz, qm, Dsel);
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// Partial Product Generation
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csa csa(WS, WC, Dsel, qp, WSA, WCA);
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// Exponent division
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exp exp(SrcXExpE, SrcYExpE, Exp);
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srtpostproc postproc(rp, rm, Quot);
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endmodule
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module srtpostproc #(parameter N=52) (
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input [N+2:0] rp, rm,
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output [N-1:0] Quot
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);
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//assign Quot = rp - rm;
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finaladd finaladd(rp, rm, Quot);
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endmodule
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module srtpreproc #(parameter Nf=52) (
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [Nf-1:0] SrcXFrac, SrcYFrac,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputss
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input logic Sqrt, // perform square root, not divide
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output logic [Nf-1:0] X, D
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);
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// Initial: just pass X and Y through for simple fp division
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assign X = SrcXFrac;
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assign D = SrcYFrac;
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endmodule
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/*
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//////////
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// mux2 //
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//////////
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module mux2(input logic [55:0] in0, in1,
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input logic sel,
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output logic [55:0] out);
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assign #1 out = sel ? in1 : in0;
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endmodule
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//////////
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// flop //
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//////////
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module flop(clk, in, out);
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input clk;
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input [55:0] in;
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output [55:0] out;
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logic [55:0] state;
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always @(posedge clk)
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state <= #1 in;
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assign #1 out = state;
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endmodule
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*/
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//////////
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// qsel //
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//////////
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module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits
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input logic [Nf+3:Nf] ps, pc,
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output logic qp, qz, qm
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);
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logic [Nf+3:Nf] p, g;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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// for efficiency. You can probably optimize your logic to
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// select the proper divisor with less delay.
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// Quotient equations from EE371 lecture notes 13-20
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign #1 magnitude = ~(&p[54:52]);
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assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
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assign #1 sign = p[55] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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assign #1 sign = (ps[55]^pc[55])^
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(ps[54] & pc[54] | ((ps[54]^pc[54]) &
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(ps[53]&pc[53] | ((ps[53]^pc[53]) &
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(ps[52]&pc[52]))))); */
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// Produce quotient = +1, 0, or -1
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assign #1 qp = magnitude & ~sign;
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assign #1 qz = ~magnitude;
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assign #1 qm = magnitude & sign;
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endmodule
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//////////
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// qacc //
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//////////
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module qacc #(parameter N=55) (
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input logic clk,
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input logic req,
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input logic qp, qz, qm,
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output logic [N-1:0] rp, rm
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);
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flopr #(N) rmreg(clk, req, {rm[53:0], qm}, rm);
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flopr #(N) rpreg(clk, req, {rp[53:0], qp}, rp);
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/* always @(posedge clk)
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begin
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if (req)
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begin
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rp <= #1 0;
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rm <= #1 0;
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end
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else
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begin
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rm <= #1 {rm[54:0], qm};
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rp <= #1 {rp[54:0], qp};
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end
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end */
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endmodule
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/////////
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// inv //
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/////////
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module inv(input logic [55:0] in,
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output logic [55:0] out);
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assign #1 out = ~in;
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endmodule
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//////////
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// mux3 //
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//////////
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module mux3onehot(in0, in1, in2, sel0, sel1, sel2, out);
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input [55:0] in0;
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input [55:0] in1;
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input [55:0] in2;
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input sel0;
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input sel1;
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input sel2;
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output [55:0] out;
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// lazy inspection of the selects
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// really we should make sure selects are mutually exclusive
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assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2);
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endmodule
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/////////
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// csa //
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/////////
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module csa #(parameter N=56) (
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input logic [N-1:0] in1, in2, in3,
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input logic cin,
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output logic [N-1:0] out1, out2
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);
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// This block adds in1, in2, in3, and cin to produce
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// a result out1 / out2 in carry-save redundant form.
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// cin is just added to the least significant bit and
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// is required to handle adding a negative divisor.
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// Fortunately, the carry (out2) is shifted left by one
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// bit, leaving room in the least significant bit to
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// insert cin.
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assign #1 out1 = in1 ^ in2 ^ in3;
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assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) |
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(in2[54:0] & in3[54:0]), cin};
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endmodule
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//////////////
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// exponent //
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//////////////
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module exp(input [10:0] e1, e2,
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output [10:0] e); // for double precision, exponent is 11 bits
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assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
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endmodule
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//////////////
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// finaladd //
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//////////////
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module finaladd(
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input logic [54:0] rp, rm,
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output logic [51:0] r
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);
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logic [54:0] diff;
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// this magic block performs the final addition for you
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// to convert the positive and negative quotient digits
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// into a normalized mantissa. It returns the 52 bit
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// mantissa after shifting to guarantee a leading 1.
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// You can assume this block operates in one cycle
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// and do not need to budget it in your area and power
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// calculations.
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// Since no rounding is performed, the result may be too
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// small by one unit in the least significant place (ulp).
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// The checker ignores such an error.
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assign #1 diff = rp - rm;
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assign #1 r = diff[54] ? diff[53:2] : diff[52:1];
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endmodule
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