forked from Github_Repos/cvw
56 lines
1.9 KiB
Systemverilog
56 lines
1.9 KiB
Systemverilog
///////////////////////////////////////////
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// simple_timer.sv
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//
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// Written: Ross Thompson September 20, 2021
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// Modified:
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//
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// Purpose: SD card controller
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module simple_timer #(parameter BUS_WIDTH = 4)
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(
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input logic [BUS_WIDTH-1:0] VALUE,
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input logic START,
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output logic FLAG,
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input logic RST,
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input logic CLK);
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logic [BUS_WIDTH-1:0] count;
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logic timer_en;
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assign timer_en = count != 0;
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always_ff @(posedge CLK, posedge RST) begin
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if (RST) begin
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count <= '0;
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end else if (START) begin
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count <= VALUE - 1'b1;
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end else if(timer_en) begin
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count <= count - 1'b1;
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end
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end
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assign FLAG = count != 0;
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endmodule
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