forked from Github_Repos/cvw
234 lines
7.2 KiB
Plaintext
234 lines
7.2 KiB
Plaintext
///////////////////////////////////////////
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// tlb_toy.sv
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//
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// Written: jtorrey@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Example translation lookaside buffer
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// Cache of virtural-to-physical address translations
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/**
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* sv32 specs
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* ----------
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* Virtual address [31:0] (32 bits)
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* [________________________________]
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* |--VPN1--||--VPN0--||----OFF---|
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* 10 10 12
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*
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* Physical address [33:0] (34 bits)
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* [__________________________________]
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* |---PPN1---||--PPN0--||----OFF---|
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* 12 10 12
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*
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* Page Table Entry [31:0] (32 bits)
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* [________________________________]
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* |---PPN1---||--PPN0--|||DAGUXWRV
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* 12 10 ^^
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* RSW(2) -- for OS
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*/
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/* *** TODO:
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* - add LRU algorithm (select the write index based on which entry was used
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* least recently)
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*/
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// The TLB will have 2**ENTRY_BITS total entries
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module tlb_toy #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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// Current value of satp CSR (from privileged unit)
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input [`XLEN-1:0] SATP, // *** How do we get this?
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// Virtual address input
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input [`XLEN-1:0] VirtualAddress,
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// Controls for writing a new entry to the TLB
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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// Invalidate all TLB entries
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input TLBFlush,
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// Physical address outputs
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output [`XLEN-1:0] PhysicalAddress,
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output TLBMiss,
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output TLBHit
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);
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generate
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if (`XLEN == 32) begin: ARCH
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localparam VPN_BITS = 20;
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localparam PPN_BITS = 22;
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localparam PA_BITS = 34;
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logic SvMode;
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assign SvMode = SATP[31]; // *** change to an enum somehow?
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end else begin: ARCH
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localparam VPN_BITS = 27;
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localparam PPN_BITS = 44;
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localparam PA_BITS = 56;
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logic SvMode; // currently just a boolean whether translation enabled
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assign SvMode = SATP[63]; // *** change to an enum somehow?
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end
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endgenerate
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// Index (currently random) to write the next TLB entry
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logic [ENTRY_BITS-1:0] WriteIndex;
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// Sections of the virtual and physical addresses
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logic [ARCH.VPN_BITS-1:0] VirtualPageNumber;
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logic [ARCH.PPN_BITS-1:0] PhysicalPageNumber;
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logic [11:0] PageOffset;
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logic [ARCH.PA_BITS-1:0] PhysicalAddressFull;
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// Pattern and pattern location in the CAM
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logic [ENTRY_BITS-1:0] VPNIndex;
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// RAM access location
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logic [ENTRY_BITS-1:0] EntryIndex;
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// Page table entry matching the virtual address
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logic [`XLEN-1:0] PageTableEntry;
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assign VirtualPageNumber = VirtualAddress[ARCH.VPN_BITS+11:12];
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assign PageOffset = VirtualAddress[11:0];
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// Choose a read or write location to the entry list
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mux2 #(3) indexmux(VPNIndex, WriteIndex, TLBWrite, EntryIndex);
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// Currently use random replacement algorithm
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tlb_rand rdm(.*);
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tlb_ram #(ENTRY_BITS) ram(.*);
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tlb_cam #(ENTRY_BITS, ARCH.VPN_BITS) cam(.*);
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always_comb begin
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assign PhysicalPageNumber = PageTableEntry[ARCH.PPN_BITS+9:10];
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if (TLBHit) begin
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assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset};
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end else begin
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assign PhysicalAddressFull = 8'b0; // *** Actual behavior; disabled until walker functioning
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//assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready
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end
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end
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generate
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if (`XLEN == 32) begin
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mux2 #(`XLEN) addressmux(VirtualAddress, PhysicalAddressFull[31:0], ARCH.SvMode, PhysicalAddress);
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end else begin
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mux2 #(`XLEN) addressmux(VirtualAddress, {8'b0, PhysicalAddressFull}, ARCH.SvMode, PhysicalAddress);
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end
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endgenerate
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assign TLBMiss = ~TLBHit & ~(TLBWrite | TLBFlush) & ARCH.SvMode;
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endmodule
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module tlb_ram #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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input [ENTRY_BITS-1:0] EntryIndex,
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input [`XLEN-1:0] PageTableEntryWrite,
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input TLBWrite,
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output [`XLEN-1:0] PageTableEntry
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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logic [`XLEN-1:0] ram [0:NENTRIES-1];
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always @(posedge clk) begin
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if (TLBWrite) ram[EntryIndex] <= PageTableEntryWrite;
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end
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assign PageTableEntry = ram[EntryIndex];
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initial begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i] = `XLEN'b0;
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end
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endmodule
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module tlb_cam #(parameter ENTRY_BITS = 3,
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parameter KEY_BITS = 20) (
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input clk, reset,
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input [KEY_BITS-1:0] VirtualPageNumber,
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input [ENTRY_BITS-1:0] WriteIndex,
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input TLBWrite,
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input TLBFlush,
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output [ENTRY_BITS-1:0] VPNIndex,
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output TLBHit
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);
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localparam NENTRIES = 2**ENTRY_BITS;
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// Each entry of this memory has KEY_BITS for the key plus one valid bit.
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logic [KEY_BITS:0] ram [0:NENTRIES-1];
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logic [ENTRY_BITS-1:0] matched_address_comb;
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logic match_found_comb;
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always @(posedge clk) begin
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if (TLBWrite) ram[WriteIndex] <= {1'b1,VirtualPageNumber};
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if (TLBFlush) begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i][KEY_BITS] = 1'b0; // Zero out msb (valid bit) of all entries
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end
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end
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// *** Check whether this for loop synthesizes correctly
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always_comb begin
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match_found_comb = 1'b0;
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matched_address_comb = '0;
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for (int i = 0; i < NENTRIES; i++) begin
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if (ram[i] == {1'b1,VirtualPageNumber} && !match_found_comb) begin
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matched_address_comb = i;
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match_found_comb = 1;
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end else begin
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matched_address_comb = matched_address_comb;
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match_found_comb = match_found_comb;
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end
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end
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end
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assign VPNIndex = matched_address_comb;
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assign TLBHit = match_found_comb & ~(TLBWrite | TLBFlush);
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initial begin
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for (int i = 0; i < NENTRIES; i++)
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ram[i] <= '0;
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end
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endmodule
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module tlb_rand #(parameter ENTRY_BITS = 3) (
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input clk, reset,
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output [ENTRY_BITS:0] WriteIndex
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);
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logic [31:0] data;
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assign data = $urandom;
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assign WriteIndex = data[ENTRY_BITS:0];
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endmodule
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